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參數(shù)資料
| 型號： | IDT72T1875L6-7BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
| 中文描述： | 2.5伏高速TeraSync先進(jìn)先出18-BIT/9-BIT配置 |
| 文件頁數(shù)： | 8/55頁 |
| 文件大?。?/td> | 540K |
| 代理商： | IDT72T1875L6-7BBI |
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8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PRS
Partial Reset
HSTL-LVTTL
PRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
INPUT
the existing mode (IDT or FWFT), programmng method (serial or parallel), and programmable flag settings
are all retained.
HSTL-LVTTL Data outputs for an 18- or 9-bit bus. When in 9-bit mode, any unused output pins should not be connected.
OUTPUT
Outputs are not 5V tolerant regardless of the state of
OE
and
RCS
.
HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by
REN
, the rising edge of RCLK
INPUT
reads data fromthe FIFO memory and offsets fromthe programmable registers. If
LD
is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been
selected, a rising edge on RD reads data fromthe FIFO in an Asynchronous manner.
REN
should be tied LOW.
Read Chip Select HSTL-LVTTL
RCS
provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During
INPUT
a Master or Partial Reset the
RCS
input is dont care, if
OE
is LOW the data outputs will be Low-Impedance
regardless of
RCS
.
Read Enable
HSTL-LVTTL If Synchronous operation of the read port has been selected,
REN
enables RCLK for reading data fromthe
INPUT
FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the
REN
input should be tied LOW.
RHSTL
(1)
Read Port HSTL
LVTTL
This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
Select
INPUT
required, this input must be tied HIGH. Otherwise it should be tied LOW.
RT
Retransmt
HSTL-LVTTL
RT
asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the
EF
flag to LOW (
OR
to HIGH
INPUT
in FWFT mode) and doesnt disturb the write pointer, programmng method, existing timng mode or programmable
flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to the mark’ location.
SCLK
Serial Clock
HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
INPUT
SEN
is enabled.
SEN
Serial Enable
HSTL-LVTTL
SEN
enables serial loading of programmable flag offsets.
INPUT
SHSTL
SystemHSTL
LVTTL
All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
Select
INPUT
TCK
(2)
JTAG Clock
HSTL-LVTTL Clock input for JTAG function. One of four termnals required by IEEE Standard 1149.1-1990. Test operations
INPUT
of the device are synchronous to TCK. Data fromTMS and TDI are sampled on the rising edge of TCK and
outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI
(2)
JTAG Test Data
HSTL-LVTTL One of four termnals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test
Input
INPUT
data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass
Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO
(2)
JTAG Test Data
HSTL-LVTTL One of four termnals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test
Output
OUTPUT
data serially loaded output via the TDO on the falling edge of TCK fromeither the Instruction Register, ID Register
and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR
controller states.
TMS
(2)
JTAG Mode
HSTL-LVTTL TMS is a serial input pin. One of four termnals required by IEEE Standard 1149.1-1990. TMS directs the
Select
INPUT
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST
(2)
JTAG Reset
HSTL-LVTTL
TRST
is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
INPUT
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use
TRST
, then
TRST
can be tied with
MRS
to ensure proper
FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.
WEN
Write Enable
HSTL-LVTTL When Synchronous operation of the write port has been selected,
WEN
enables WCLK for writing data into
INPUT
the FIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the
WEN
input should be tied LOW.
WCS
Write Chip Select HSTL-LVTTL The
WCS
pin can be regarded as a second
WEN
input, enabling/disabling write operations.
INPUT
WCLK/
Write Clock/
HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by
WEN
, the rising edge of WCLK
WR
Write Strobe
INPUT
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into
the FIFO on a rising edge in an Asynchronous manner, (
WEN
should be tied to its active state).
Q
0
–Q
17
Data Outputs
RCLK/
RD
Read Clock/
Read Strobe
RCS
REN
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O TYPE
Description
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