參數資料
型號： IDT72T20108L7BB
廠商： Integrated Device Technology, Inc.
英文描述： 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
中文描述： 2.5伏高速TeraSync⑩復員/特別提款權先進先出20-BIT/10-BIT配置
文件頁數： 18/51頁
文件大小： 496K
代理商： IDT72T20108L7BB
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
PAF
flags will not be updated. The write and read clocks can either be
independent or coincident.
WRITE ENABLE (
WEN
)
When the
WEN
input is LOW, data may be loaded into the FIFO RAMarray
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAMarray sequentially and independently of any ongoing read opera-
tion.
When
WEN
is HIGH, no new data is written in the RAMarray on each
WCLK cycle.
To prevent data overflow in the IDT Standard mode,
FF
will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF
will go HIGH, allowing a write to occur. The
FF
is updated by two WCLK
cycles + t
SKEW
after the RCLK cycle.
To prevent data overflow in the FWFT mode,
IR
will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle,
IR
will go
LOW, allowing a write to occur. The
IR
flag is updated by two WCLK cycles +
t
SKEW
after the valid RCLK cycle.
WEN
is ignored when the FIFO is full in either IDT Standard mode or
FWFT.
WRITE SINGLE DATA RATE (
WSDR
)
When the Write Single Data Rate pin is LOW, the write port will be set to
Single Data Rate mode. In this mode, all write operations are based only on
the rising edge of WCLK, provided that
WEN
and
WCS
are LOW. When
WSDR
is HIGH, the read port will be set to Double Data Rate mode. In this
mode, all write operations are based on both the rising and falling edge of
WCLK, provided that
WEN
and
WCS
are LOW, on the rising edge of WCLK.
READ CLOCK (RCLK)
A read cycle is initiated on the rising and/or falling edge of the RCLK input.
If the Read Single Data Rate (
RSDR
) pin is selected, data will be read only on
the rising edge of RCLK, provided that
REN
and
RCS
are LOW. If the
RSDR
is not selected, data will be read on both the rising and falling edge of WCLK,
provided that
REN
and
RCS
are LOW, on the rising edge of RCLK. Setup and
hold times must be met with respect to the LOW-to-HIGH transition of the
RCLK. It is permssible to stop the RCLK. Note that while RCLK is idle, the
EF
/
OR
and
PAE
flags will not be updated. Write and Read Clocks can be inde-
pendent or coincident.
READ ENABLE (
REN
)
When Read Enable is LOW, data is loaded fromthe RAMarray into the
output register on the rising edge of every RCLK cycle if the device is not
empty.
When the
REN
input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In IDT Standard mode, every word accessed at Qn, including the first word
written to an empty FIFO, must be requested using
REN
provided that the
Read Chip Select (
RCS
) is LOW. When the last word has been read fromthe
FIFO, the Empty Flag (
EF
) will go LOW, inhibiting further read operations.
REN
is ignored when the FIFO is empty. Once a write is performed,
EF
will go
HIGH allowing a read to occur. Both
RCS
and
REN
must be active LOW for
data to be read out on the rising edge of RCLK.
In FWFT mode, the first word written to an empty FIFO automatically goes
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + t
SKEW
after the first write.
REN
and
RCS
do not need to be asserted LOW for the First
Word to fall through to the output register. All subsequent words require that a
read operation to be executed using
REN
and
RCS
. The LOW-to-HIGH
transition of RCLK after the last word has been read fromthe FIFO will make
Output Ready (
OR
) go HIGH with a true read (RCLK with
REN
and
RCS
LOW), inhibiting further read operations.
REN
is ignored when the FIFO is
empty.
READ SINGLE DATA RATE (
RSDR
)
When the Read Single Data Rate pin is LOW, the read port will be set to
Single Data Rate mode. In this mode, all read operations are based only on
the rising edge of RCLK, provided that
REN
and
RCS
are LOW. When
RSDR
is HIGH, the read port will be set to Double Data Rate mode. In this mode, all
read operations are based on both the rising and falling edge of RCLK,
provided that
REN
and
RCS
are LOW, on the rising edge of RCLK.
SERIAL CLOCK (SCLK)
The serial clock is used to load and read data in the programmable offset
registers. Data fromthe Serial Input (SI) can be loaded into the offset registers
on the rising edge of SCLK provided that
SEN
is LOW. Data can be read from
the offset registers via the Serial Output (SO) on the rising edge of SCLK
provided that
SREN
is LOW. The serial clock can operate at a maximum
frequency of 10MHz and its parameters are different than the FIFO system
clock.
SERIAL ENABLE (
SEN
)
The
SEN
input is an enable used for serial programmng of the program-
mable offset registers. It is used in conjunction with SI and SCLK when pro-
grammng the offset registers. When
SEN
is LOW, data at the Serial In (SI)
input can be loaded into the offset register, one bit for each LOW-to-HIGH
transition of SCLK.
When
SEN
is HIGH, the offset registers retain the previous settings and no
offsets are loaded.
SEN
functions the same way in both IDT Standard and
FWFT modes.
SERIAL READ ENABLE (
SREN
)
The
SREN
output is an enable used for reading the value of the program-
mable offset registers. It is used in conjunction with SI and SCLK when reading
fromthe offset registers. When
SREN
is LOW data can be read out of the offset
register fromthe SO output, one bit for each LOW-to-HIGH transition of SCLK.
When
SREN
is HIGH, the reading of the offset registers will stop. When-
ever
SREN
is activated values in the offset registers are read starting fromthe
first location in the offset registers and not fromwhere the last offset value was
read.
SREN
functions the same way in both IDT Standard and FWFT modes.
SERIAL IN (SI)
This pin acts as a serial input for loading
PAE
and
PAF
offsets into the
programmable offset registers. It is used in conjunction with the Serial Clock
(SCLK) and the Serial Enable (
SEN
). Data fromthis input can be loaded into
the offset register, one bit for each LOW-to-HIGH transition of SCLK provided
that
SEN
is LOW.
SERIAL OUT (SO)
This pin acts as a serial output for reading the values of the
PAE
and
PAF
offsets in the programmable offset registers. It is used in conjunction with the
Serial Clock (SCLK) and the Serial Enable Output (
SREN
). Data fromthe
offset register can be read out using this pin, one-bit for each LOW-to-HIGH
transition of SCLK provided that
SREN
is LOW.
相關PDF資料
PDF描述
IDT72T20108L7BBI 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20118 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20118L10BB 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20118L10BBI 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
IDT72T20118L4BB 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
相關代理商/技術參數
參數描述
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IDT72T20118L6-7BB 功能描述:IC FIFO 65536X20 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數據速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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