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參數(shù)資料
| 型號： | IDT72T20108L7BB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| 中文描述： | 2.5伏高速TeraSync⑩復(fù)員/特別提款權(quán)先進(jìn)先出20-BIT/10-BIT配置 |
| 文件頁數(shù)： | 4/51頁 |
| 文件大小： | 496K |
| 代理商： | IDT72T20108L7BB |
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4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
DESCRIPTION (CONTINUED)
(SI) pin at the rising edge of SCLK. To read out the offset registers serially, set
SREN
active and data can be read out via the Serial Output (SO) pin at the rising
edge of SCLK. Four default offset settings are also provided, so that
PAE
can
be marked at a predefined number of locations fromthe empty boundary and
the
PAF
threshold can also be marked at simlar predefined values fromthe full
boundary. The default offset values are set during Master Reset by the state
of the FSEL0 and FSEL1 pins.
During Master Reset (
MRS
), the following events occur: the read and write
pointers are set to the first location of the internal FIFO memory, the FWFT pin
selects IDT Standard mode or FWFT mode, the bus width configuration of the
read and write port is determned by the state of IW and OW, and the default offset
values for the programmable flags are set.
The Partial Reset (
PRS
) also sets the read and write pointers to the first
location of the memory. However, the timng mode and the values stored in the
programmable offset registers before Partial Reset remain unchanged. The
flags are updated according to the timng mode and offsets in effect.
PRS
is useful
for resetting a device in md-operation, when reprogrammng programmable
flags would be undesirable.
The timng of the
PAE
and
PAF
flags are synchronous to RCLK and WCLK,
respectively. The
PAE
flag is asserted upon the rising edge of RCLK only and
not WCLK. Simlarly the
PAF
is asserted and updated on the rising edge of
WCLK only and not RCLK.
This device includes a Retransmt fromMark feature that utilizes two control
inputs, MARK and
RT
(Retransmt). If the MARK input is enabled with respect
to the RCLK, the memory location being read at the point will be marked. Any
subsequent retransmt operation (when
RT
goes LOW), will reset the read
pointer to this “marked” location.
The device can be configured with different input and output bus widths as
previously stated. These rates are: x20 to x20, x20 to x10, x10 to x20 and x10
to x10.
If, at any time, the FIFO is not actively performng an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is mnimzed. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
A JTAG test port is provided, here the FIFO has fully functional boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
The Double Data Rate FIFO has the capability of operating in either LVTTL
or HSTL mode. HSTL mode can be selected by enabling the HSTL pin. Both
input and output ports will operate in either HSTL or LVTTL mode, but cannot
be selected independent of one another.
The IDT72T2098/72T20108/72T20118/72T20128 are fabricated using
IDT’s high-speed submcron CMOS technology.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T20108L7BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20118 | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20118L10BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20118L10BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T20118L4BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T20118L10BB | 功能描述:IC FIFO 65536X20 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L4BB | 功能描述:IC FIFO 65536X20 4NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L5BB | 功能描述:IC FIFO 65536X20 5NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20118L6-7BB | 功能描述:IC FIFO 65536X20 6-7NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T20128L10BB | 功能描述:IC FIFO 1KX20 2.5V 10NS 208BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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