參數(shù)資料
型號(hào)： IDT72T36125L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
中文描述： 256K X 36 OTHER FIFO, 3.6 ns, PBGA240
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-240
文件頁(yè)數(shù)： 22/57頁(yè)
文件大?。?/td> 556K
代理商： IDT72T36125L5BB
22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
When a 36 bit output bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125, 2 enabled read cycles are required to read
the offset registers, (1 per offset). Data on the outputs Qn are read fromthe Empty
Offset Register on the first LOW-to-HIGH transition of RCLK. Upon the second
LOW-to-HIGH transition of RCLK, data are read fromthe Full Offset Register.
The third transition of RCLK reads, once again, fromthe Empty Offset Register.
When an 18 bit output bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105, 2 enabled read cycles are required to read the offset registers, (1
per offset). Data on the outputs Qn are read fromthe Empty Offset Register on
the first LOW-to-HIGH transition of RCLK. Upon the second LOW-to-HIGH
transition of RCLK, data are read fromthe Full Offset Register. The third transition
of RCLK reads, once again, fromthe Empty Offset Register.
For the IDT72T36115/72T36125, 4 enabled read cycles are required to
read the offset registers, (2 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Upon the 2
nd
LOW-to-HIGH transition of RCLK data on the outputs Qn are read
fromthe Empty Offset Register MSB. Upon the 3
rd
LOW-to-HIGH transition of
RCLK data on the outputs Qn are read fromthe Full Offset Register LSB. Upon
the 4
th
LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
the Full Offset Register MSB. The 5
th
LOW-to-HIGH transition of RCLK data on
the outputs Qn are once again read fromthe Empty Offset Register LSB.
When a 9 bit output bus width is used:
For the IDT72T36115/72T36125, 4 enabled read cycles are required to
read the offset registers, (2 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Upon the 2
nd
LOW-to-HIGH transition of RCLK data on the outputs Qn are read
fromthe Empty Offset Register MSB. Upon the 3
rd
LOW-to-HIGH transition of
RCLK data on the outputs Qn are read fromthe Full Offset Register LSB. Upon
the 4
th
LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
the Full Offset Register MSB. The 5
th
LOW-to-HIGH transition of RCLK data on
the outputs Qn are once again read fromthe Empty Offset Register LSB.
For the IDT72T36115/72T36125, 6 enabled read cycles are required to
read the offset registers, (3 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Upon the 3
rd
LOW-to-HIGH transition of RCLK data on the outputs Qn are read
fromthe Empty Offset Register MSB. Upon the 4
th
LOW-to-HIGH transition of
RCLK data on the outputs Qn are read fromthe Full Offset Register LSB. Upon
the 6
th
LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
the Full Offset Register MSB. The 7
th
LOW-to-HIGH transition of RCLK data on
the outputs Qn are once again read fromthe Empty Offset Register LSB. See
Figure 3,
Programmable Flag Offset Programmng Sequence
. See Figure
22,
Parallel Read of Programmable Flag Registers
, for the timng diagramfor
this mode.
It is permssible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting
REN
,
LD
,
or both together. When
REN
and
LD
are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken fromthe fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permtted regardless of
which timng mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT FROMMARK OPERATION
The Retransmt fromMark feature allows FIFO data to be read repeatedly
starting at a user-selected position. The FIFO is first put into retransmt mode that
will mark’ a beginning word and also set a pointer that will prevent ongoing FIFO
write operations fromover-writing retransmt data. The retransmt data can be
read repeatedly any number of times fromthe marked position. The FIFO can
be taken out of retransmt mode at any time to allow normal device operation.
The mark’ position can be selected any number of times, each selection over-
writing the previous mark location. Retransmt operation is available in both IDT
standard and FWFT modes.
During IDT standard mode the FIFO is put into retransmt mode by a Low-
to-High transition on RCLK when the MARK’ input is HIGH and
EF
is HIGH.
The rising RCLK edge marks’ the data present in the FIFO output register as
the first retransmt data. The FIFO remains in retransmt mode until a rising edge
on RCLK occurs while MARK is LOW.
Once a marked location has been set (and the device is still in retransmt
mode, MARK is HIGH), a retransmt can be initiated by a rising edge on RCLK
while the retransmt input (
RT
) is LOW.
REN
must be HIGH (reads disabled)
before bringing
RT
LOW. The device indicates the start of retransmt setup by
setting
EF
LOW, also preventing reads. When
EF
goes HIGH, retransmt setup
is complete and read operations may begin starting with the first data at the MARK
location. Since IDT standard mode is selected, every word read including the
first marked word following a retransmt setup requires a LOW on
REN
(read
enabled).
Note, write operations may continue as normal during all retransmt
functions, however write operations to the marked location will be prevented.
See Figure 18,
Retransmt fromMark (IDT standard mode)
, for the relevant
timng diagram
During FWFT mode the FIFO is put into retransmt mode by a rising RCLK
edge when the MARK’ input is HIGH and
OR
is LOW. The rising RCLK edge
‘marks’ the data present in the FIFO output register as the first retransmt data.
The FIFO remains in retransmt mode until a rising RCLK edge occurs while
MARK is LOW.
Once a marked location has been set (and the device is still in retransmt
mode, MARK is HIGH), a retransmt can be initiated by a rising RCLK edge while
the retransmt input (
RT
) is LOW.
REN
must be HIGH (reads disabled) before
bringing
RT
LOW. The device indicates the start of retransmt setup by setting
OR
HIGH.
When
OR
goes LOW, retransmt setup is complete and on the next rising
RCLK edge after retransmt setup is complete, (
RT
goes HIGH), the contents
of the first retransmt location are loaded onto the output register. Since FWFT
mode is selected, the first word appears on the outputs regardless of
REN
, a
LOW on
REN
is not required for the first word. Reading all subsequent words
requires a LOW on
REN
to enable the rising RCLK edge. See Figure 19,
Retransmt fromMark timng (FWFT mode)
, for the relevant timng diagram
Note, there must be a mnimumof 32 bytes of data between the write pointer
and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long
words). Also, once the MARK is set, the write pointer will not increment past the
“marked” location until the MARK is deasserted. This prevents “overwriting”
of retransmt data.
HSTL/LVTTL I/O
Both the write port and read port are user selectable between HSTL or
LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other
control pins are selectable via SHSTL, see Table 5 for details of groupings.
Note, that when the write port is selected for HSTL mode, the user can reduce
the power consumption (in stand-by mode by utilizing the
WCS
input).
All “Static Pins” must be tied to V
CC
or GND. These pins are LVTTL only,
and are purely device configuration pins.
相關(guān)PDF資料
PDF描述
IDT72T3645L4BB 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
IDT72T3655L4BB 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
IDT72T3665L4BB 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
IDT72T3695L4BB 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
IDT72T36125L4BB 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T36125L5BBG 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36125L5BBGI 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36125L5BBI 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36125L6-7BB 功能描述:IC FIFO 524X18 6-7NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36135ML5BB 功能描述:IC FIFO 1MX18 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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