參數(shù)資料
型號(hào)： IDT72T36125L5BB
廠(chǎng)商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
中文描述： 256K X 36 OTHER FIFO, 3.6 ns, PBGA240
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-240
文件頁(yè)數(shù)： 7/57頁(yè)
文件大?。?/td> 556K
代理商： IDT72T36125L5BB
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PIN DESCRIPTION
Symbol
Name
ASYR
(1)
Asynchronous
Read Port
ASYW
(1)
Asynchronous
Write Port
BE
(1)
Big-Endian/
Little-Endian
BM
(1)
Bus-Matching
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
HSTL-LVTTL Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins should be tied to GND.
INPUT
HSTL-LVTTL In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or not the FIFO memory is empty.
OUTPUT
In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is valid data available at the
outputs.
HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
Full Flag/
HSTL-LVTTL In the IDT Standard mode, the
FF
function is selected.
FF
indicates whether or not the FIFO memory is
Input Ready
OUTPUT
full. In the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available for
writing to the FIFO memory.
FSEL0
(1)
Flag Select Bit 0
LVTTL
During Master Reset, this input along with FSEL1 and the
LD
pin, will select the default offset values for the
INPUT
programmable flags
PAE
and
PAF
. There are up to eight possible settings available.
FSEL1
(1)
Flag Select Bit 1
LVTTL
During Master Reset, this input along with FSEL0 and the
LD
pin will select the default offset values for the
INPUT
programmable flags
PAE
and
PAF
. There are up to eight possible settings available.
FWFT/
First Word Fall
HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
SI
Through/Serial In
INPUT
functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been
selected then the FIFO must be set-up in IDT Standard mode.
HF
Half-Full Flag
HSTL-LVTTL
HF
indicates whether the FIFO memory is more or less than half-full.
OUTPUT
IP
(1)
Interspersed Parity
LVTTL
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
INPUT
Parity mode.
IW
(1)
Input Width
LVTTL
This pin, along with OW and BM selects the bus width of the write port. See Table 1 for bus size configuration.
INPUT
LD
Load
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the
LD
input along with FSEL0 and FSEL1,
INPUT
determnes one of eight default offset values for the
PAE
and
PAF
flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing
to and reading fromthe offset registers.THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROMTHE FIFO MEMORY.
MARK
Mark for Retransmt HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmt
INPUT
operation will reset the read pointer to this position.
MRS
Master Reset
HSTL-LVTTL
MRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During Master
INPUT
Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings,
serial or parallel programmng of the offset settings, Big-Endian/Little-Endian format, zero latency timng mode,
interspersed parity, and synchronous versus asynchronous programmable flag timng modes.
OE
Output Enable
HSTL-LVTTL
OE
provides Asynchronous three-state control of the data outputs, Q
n.
During a Master or Partial Reset the
INPUT
OE
input is the only input that provide High-Impedance control of the data outputs.
OW
(1)
Output Width
LVTTL
This pin, along with IW and BM selects the bus width of the read port. See Table 1 for bus size configuration.
INPUT
PAE
Programmable
HSTL-LVTTL
PAE
goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty
Almost-Empty Flag
OUTPUT
Offset register.
PAE
goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF
Programmable
HSTL-LVTTL
PAF
goes HIGH if the number of free locations in the FIFO memory is more than offset m which is stored in the
Almost-Full Flag
OUTPUT
Full Offset register.
PAF
goes LOW if the number of free locations in the FIFO memory is less than or equal to m
PFM
(1)
Programmable
LVTTL
During Master Reset, a LOW on PFMwill select Asynchronous Programmable flag timng mode. A HIGH on
Flag Mode
INPUT
PFMwill select Synchronous Programmable flag timng mode.
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
will select Asynchronous operation.
During Master Reset, a LOW on
BE
will select Big-Endian operation. A HIGH on
BE
during Master Reset
will select Little-Endian format.
BMworks with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
configuration.
D
0
–D
35
Data Inputs
EF
/
OR
Empty Flag/
Output Ready
ERCLK RCLK Echo
EREN
FF
/
IR
I/O TYPE
Description
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相關(guān)代理商/技術(shù)參數(shù)
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IDT72T36125L5BBG 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:是 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT72T36125L5BBGI 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:是 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT72T36125L5BBI 功能描述:IC FIFO 524X18 5NS 240BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT72T36125L6-7BB 功能描述:IC FIFO 524X18 6-7NS 240BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
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