參數(shù)資料
型號(hào)： IDT72T36125L6BBI
廠商： Integrated Device Technology, Inc.
英文描述： 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
中文描述： 2.5伏高速TeraSyncTM FIFO的36位配置
文件頁(yè)數(shù)： 26/57頁(yè)
文件大?。?/td> 556K
代理商： IDT72T36125L6BBI
26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
into a high impedance state. During Master or a Partial Reset the
OE
is the only
input that can place the output bus Qn, into High-Impedance. During Reset the
RCS
input can be HIGH or LOW, it has no effect on the Qn outputs.
READ CHIP SELECT (
RCS
)
The Read Chip Select input provides synchronous control of the Read
output port. When
RCS
goes LOW, the next rising edge of RCLK causes the
Qn outputs to go to the Low-Impedance state. When
RCS
goes HIGH, the next
RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master
or Partial Reset the
RCS
input has no effect on the Qn output bus,
OE
is the only
input that provides High-Impedance control of the Qn outputs. If
OE
is LOW the
Qn data outputs will be Low-Impedance regardless of
RCS
until the first rising
edge of RCLK after a Reset is complete. Then if
RCS
is HIGH the data outputs
will go to High-Impedance.
The
RCS
input does not effect the operation of the flags. For example, when
the first word is written to an empty FIFO, the
EF
will still go fromLOW to HIGH
based on a rising edge of RCLK
,
regardless of the state of the
RCS
input.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of
RCS
. For this reason the user must take care when
a data word is written to an empty FIFO in FWFT mode. If
RCS
is disabled when
an empty FIFO is written into, the first word will fall through to the output register,
but will not be available on the Qn outputs which are in HIGH-Z. The user must
take
RCS
active LOW to access this first word, place the output bus in LOW-Z.
REN
must remain disabled HIGH for at least one cycle after
RCS
has gone LOW.
A rising edge of RCLK with
RCS
and
REN
active LOW, will read out the next
word. Care must be taken so as not to lose the first word written to an empty
FIFO when
RCS
is HIGH. Refer to Figure 17,
RCS
and
REN
Read Operation
(FWFT Mode).
The
RCS
pin must also be active (LOW) in order to perform
a Retransmt. See Figure 13 for
Read Cycle and Read Chip Select Timng (IDT
Standard Mode).
See Figure 16 for
Read Cycle and Read Chip Select Timng
(First Word Fall Through Mode).
If Asynchronous operation of the Read port has been selected, then
RCS
must be held active, (tied LOW).
OE
provides three-state control of Qn.
WRITE PORT HSTL SELECT (WHSTL)
The control inputs, data inputs and flag outputs associated with the write port
can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master
Reset, then HSTL operation of the write port will be selected. If WHSTL is LOW
at Master Reset, then LVTTL will be selected.
The inputs and outputs associated with the write port are listed in Table 5.
READ PORT HSTL SELECT (RHSTL)
The control inputs, data inputs and flag outputs associated with the read port
can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master
Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW
at Master Reset, then LVTTL will be selected for the read port, then echo clock
and echo read enable will not be provided.
The inputs and outputs associated with the read port are listed in Table 5.
SYSTEMHSTL SELECT (SHSTL)
All inputs not associated with the write and read port can be setup to be either
HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation
of all the inputs not associated with the write and read port will be selected. If
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs
associated with SHSTL are listed in Table 5.
LOAD (
LD
)
This is a dual purpose pin. During Master Reset, the state of the
LD
input,
along with FSEL0 and FSEL1, determnes one of eight default offset values for
the
PAE
and
PAF
flags, along with the method by which these offset registers
can be programmed, parallel or serial (see Table 2). After Master Reset,
LD
enables write operations to and read operations fromthe offset registers. Only
the offset loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel.
After Master Reset, the
LD
pin is used to activate the programmng process
of the flag offset values
PAE
and
PAF
. Pulling
LD
LOW will begin a serial loading
or parallel load or read of these offset values. THIS PIN MUST BE HIGH
AFTER MASTER RESET TO WRITE OR READ DATA TO/FROMTHE FIFO
MEMORY.
BUS-MATCHING (BM IW, OW)
The pins BM IW and OW are used to define the input and output bus widths.
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 5 for
Bus-
Matching Byte Arrangement
.
BIG-ENDIAN/LITTLE-ENDIAN (
BE
)
During Master Reset, a LOW on
BE
will select Big-Endian operation. A
HIGH on
BE
during Master Reset will select Little-Endian format. This function
is useful when the following input to output bus widths are implemented: x36 to
x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (
BE
) pin. See
Figure 5 for
Bus-Matching Byte Arrangement
.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFMwill select Asynchronous Program-
mable flag timng mode. A HIGH on PFMwill select Synchronous Program-
mable flag timng mode. If asynchronous
PAF
/
PAE
configuration is selected
(PFM LOW during
MRS
), the
PAE
is asserted LOW on the LOW-to-HIGH
transition of RCLK.
PAE
is reset to HIGH on the LOW-to-HIGH transition of
WCLK. Simlarly, the
PAF
is asserted LOW on the LOW-to-HIGH transition of
WCLK and
PAF
is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous
PAE
/
PAF
configuration is selected (PFM HIGH during
MRS) , the
PAE
is asserted and updated on the rising edge of RCLK only and
not WCLK. Simlarly,
PAF
is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by
the state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
During Master Reset, a LOW on IP will select Non-Interspersed Parity
mode. A HIGH will select Interspersed Parity mode. The IP bit function allows
the user to select the parity bit in the word loaded into the parallel port (D
0
-Dn)
when programmng the flag offsets. If Interspersed Parity mode is selected, then
the FIFO will assume that the parity bits are located in bit position D
8
, D
17
, D
26
and D
35
during the parallel programmng of the flag offsets. If Non-Interspersed
Parity mode is selected, then D
8
, D
17
and D
28
are is assumed to be valid bits
and D
32
, D
33
, D
34
and D
35
are ignored. IP mode is selected during Master
Reset by the state of the IP input pin.
相關(guān)PDF資料
PDF描述
IDT72T51253L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51253L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51253L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51233 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51233L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T36135ML5BB 功能描述:IC FIFO 1MX18 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36135ML5BBG 功能描述:IC FIFO 1MX18 5NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36135ML6BB 功能描述:IC FIFO 1MX18 6NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36135ML6BBI 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512KX36 ASYNC 240BGA
IDT72T3645L4-4BB 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱:72271LA10PF
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*