參數(shù)資料
型號(hào): IDT72T51243L5BB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
中文描述: 64K X 18 OTHER FIFO, 3.6 ns, PBGA256
封裝: 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁(yè)數(shù): 27/55頁(yè)
文件大?。?/td> 544K
代理商: IDT72T51243L5BB
27
IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ECHO READ CLOCK (ERCLK)
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
selectable via IOSEL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of
REN
and RADEN.
The ERCLK output follows the RCLK input with an associated delay. This
delay provides the user with a more effective read clock source when reading
data fromthe Qn outputs. This is especially helpful at high speeds when variables
within the device may cause changes in the data access times. These variations
in access time maybe caused by ambient temperature, supply voltage, device
characteristics. The ERCLK output also compensates for any trace length
delays between the Qn data outputs and receiving devices inputs.
Any variations effecting the data access time will also have a corresponding
effect on the ERCLK output produced by the queue device, therefore the ERCLK
output level transitions should always be at the same position in time relative to
the data outputs. Note, that ERCLK is guaranteed by design to be slower than
the slowest Qn, data output. Refer to Figure 3,
Echo Read Clock and Data
Output Relationship
and Figure 23,
Echo RCLK & Echo
REN
Operation
for
timng information.
ECHO READ ENABLE (
EREN
)
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
selectable via IOSEL.
The
EREN
output is provided to be used in conjunction with the ERCLK
output and provides the reading device with a more effective scheme for reading
data fromthe Qn output port at high speeds. The
EREN
output is controlled by
internal logic that behaves as follows: The
EREN
output is active LOW for the
RCLK cycle that a new word is read out of the queue. That is, a rising edge of
RCLK will cause
EREN
to go active (LOW) if
REN
is active and the queue is
NOT empty.
Figure 3. Echo Read Clock and Data Output Relationship
NOTES:
1.
REN
is LOW.
OE
is LOW.
2. t
ERCLK
> t
A
, guaranteed by design.
3. Qslowest is the data output with the slowest access time, t
A
.
4. Time, t
D
is greater than zero, guaranteed by design.
6115 drw08
ERCLK
t
A
t
D
Q
SLOWEST
(3)
RCLK
t
ERCLK
t
ERCLK
相關(guān)PDF資料
PDF描述
IDT72T51243L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51243L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51243L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51253 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51253L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
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