參數(shù)資料
型號(hào)： IDT72T51253L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
中文描述： 128K X 18 OTHER FIFO, 3.6 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁(yè)數(shù)： 37/55頁(yè)
文件大小： 544K
代理商： IDT72T51253L5BB
37
IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 14. Output Valid Flag Timing (In Expansion Mode)
6115 drw18
t
AH
t
AS
t
QH
t
QS
t
ROV
D
1
Q
2
t
ROV
t
OVHZ
t
SKEW1
t
AH
t
AS
D
1
Q
2
t
QH
t
QS
t
DH
t
DS
D
1
Q
2
W
0
t
A
D
1
Q
3
W
D
Last Word
t
OLZ
t
A
D
1
Q
2
PFT W
e-1
t
A
D
1
Q
2
W
e
Last Word
t
A
W
0
Q
2
D
1
t
OVLZ
t
ROV
t
ROV
t
ENS
t
ENH
*D*
*E*
*F*
*G*
*H*
*I*
*J*
RCLK
RADEN
t
QH
t
QS
t
AH
t
AS
RDADD
D
1
Q
3
(Device 1)
t
ENS
REN
Qout
(Device 1)
HIGH-Z
WCLK
(Device 2)
WRADD
WADEN
Din
WEN
*A*
*B*
*C*
Addr=00111
Addr=00110
Addr=00110
Cycle:
*A*
Queue 3 of Device 1 is selected for read operations. The
OV
is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control
of Qout bus, its Qout outputs are in Low-Impedance. This diagramonly shows the Qout outputs of device 1. (Reads are disabled).
*B*
Reads are now enabled. A word fromthe previously selected queue of Device 2 will be read out.
*C*
After a queue switch, there is a 3 RCLK latency for output data.
*D*
The Qout of Device 1 goes to Low-Impedance and word Wd is read fromQ3 of D1. This happens to be the last word of Q3. Device 2 places its Qout outputs into
High-Impedance, device 1 has control of the Qout bus. The
OV
flag of Device 2 goes to High-Impedance and Device 1 takes control of
OV
. The
OV
flag of Device 1 goes LOW
to show that Wd of Q3 is valid.
*E*
Queue 2 of device 1 is selected for read operations. The last word of Q3 was read on the previous cycle, therefore
OV
goes HIGH to indicate that the data on the Qout is
not valid (Q3 was read to empty). Word, Wd remains on the output bus.
*F*
The last word of Q3 remains on the Qout bus,
OV
is HIGH, indicating that this word has been previously read.
*G*
The next word (We-1), available fromthe newly selected queue, Q2 of device 1 is now read out. This will occur regardless of
REN
, 2 RCLK cycles after queue selection
due to the FWFT operation. The
OV
flag updates 3 RCLK cycles after a queue selection.
*H*
The last word, We is read fromQ2, this queue is now empty.
*I*
The
OV
flag goes HIGH to indicate that Q2 was read to empty on the previous cycle.
*J *
Due to a write operation the
OV
flag goes LOW and data word W0 is read fromQ2. The latency is: t
SKEW1
+ 1*RCLK + t
ROV
.
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