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| 型號： | IDT72T51253L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 128K X 18 OTHER FIFO, 3.6 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 6/55頁 |
| 文件大?。?/td> | 544K |
| 代理商： | IDT72T51253L5BB |
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6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
D[17:0]
Din (See Pin
table for details)
DF
(1)
(L3)
Data Input Bus
HSTL-LVTTL These are the 18 data input pins. Data is written into the device via these input pins on the rising edge
INPUT
of WCLK provided that
WEN
is LOW. Due to bus matching not all inputs may be used, any unused inputs
should be tied LOW.
LVTTL
If the user requires default programmng of the multi-queue device, this pin must be setup before Master
INPUT
Reset and must not toggle during any device operation. The state of this input at master reset determnes
the value of the
PAE
/
PAF
flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
LVTTL
The multi-queue device requires programmng after master reset. The user can do this serially via the
INPUT
serial port, or the user can use the default method. If DFMis LOW at master reset then serial mode will be
selected, if HIGH then default mode is selected.
HSTL-LVTTL Read Clock Echo output, this output generates a clock based on the read clock input, this is used for Source
OUTPUT
Synchronous clocking where the receiving devices utilizes the ERCLK to clock data output fromthe queue.
HSTL-LVTTL Read Enable Echo output, can be used in conjunction with the ERCLK output to load data output fromthe
OUTPUT
queue into the receiving device.
LVTTL
If direct operation of the
PAE
n bus has been selected, the ESTR input is used in conjunction with RCLK
INPUT
and the RDADD bus to select a device for its queues to be placed on to the
PAE
n bus outputs. A device
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a
PAE
n flag bus
selection cannot be made, (ESTR must NOT go active) until programmng of the part has been completed
and
SENO
has gone LOW.
PAE
n Bus Sync HSTL-LVTTL ESYNC is an output fromthe multi-queue device that provides a synchronizing pulse for the
PAE
n bus
OUTPUT
during Polled operation of the
PAE
n bus. During Polled operation each device's queue status flags are
loaded on to the
PAE
n bus outputs sequentially based on RCLK. The first RCLK rising edge loads
device 1 onto
PAE
n, the second RCLK rising edge loads device 2 and so on. During the RCLK cycle
that a selected device is placed on to the
PAE
n bus, the ESYNC output will be HIGH.
PAE
n Bus
LVTTL
The EXI input is used when multi-queue devices are connected in expansion mode and Polled
PAE
n
Expansion In
INPUT
bus operation has been selected . EXI of device ‘N connects directly to EXO of device ‘N-1’. The EXI
receives a token fromthe previous device in a chain. In single device mode the EXI input must be tied
LOW if the
PAE
n bus is operated in direct mode. If the
PAE
n bus is operated in polled mode the EXI input
must be connected to the EXO output of the same device. In expansion mode the EXI of the first device
should be tied LOW, when direct mode is selected.
PAE
n Bus
LVTTL
EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
Expansion Out
OUTPUT
PAE
n bus operation has been selected . EXO of device N connects directly to EXI of device N+1’. This
pin pulses when device N places its
PAE
status on to the
PAE
n bus with respect to RCLK. This pulse
(token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising edge the
first quadrant of device N+1 will be loaded on to the
PAE
n bus. This continues through the chain and
EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each device
in the chain provides synchronization to the user of this looping event.
Full Flag
HSTL-LVTTL This pin provides the full flag output for the active queue, that is, the queue selected on the input
OUTPUT
port for write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after
a queue selection, this flag will show the status of the newly selected queue. Data can be written to
this queue on the next cycle provided
FF
is HIGH. This flag has High-Impedance capability, this is
important during expansion of devices, when the
FF
flag output of up to 8 devices may be connected
together on a common line. The device with a queue selected takes control of the
FF
bus, all other
devices place their
FF
output into High-Impedance. When a queue selection is made on the write
port this output will switch fromHigh-Impedance control on the next WCLK cycle. This flag is synchronized
to WCLK.
Flag Mode
HSTL-LVTTL This pin is setup before a master reset and must not toggle during any device operation. The state of the
INPUT
FMpin during Master Reset will determne whether the
PAF
n and
PAE
n flag busses operate in either
Polled or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.
Default Flag
DFM
(1)
(L2)
Default Mode
ERCLK
(R10)
EREN
(R11)
ESTR
(R15)
RCLK Echo
REN
Echo
PAE
n Flag Bus
Strobe
ESYNC
(R16)
EXI
(T16)
EXO
(T15)
FF
(P8)
FM
(1)
(K16)
PIN DESCRIPTIONS
Symbol &
Pin No.
Name
I/O TYPE
Description
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