參數(shù)資料
型號： IDT72T54242
廠商： Integrated Device Technology, Inc.
英文描述： 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述： 2.5V的四/雙TeraSync⑩復(fù)員/特別提款權(quán)先進先出× 10的四雙FIFO或x10/x20先進先出配置
文件頁數(shù)： 27/56頁
文件大小： 555K
代理商： IDT72T54242
27
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
6158 drw11
ERCLK
t
A
t
D
Q
SLOWEST
(3)
RCLK
t
ERCLK
is asserted LOW on the LOW-to-HIGH transitions of the Write Clock (WCLK).
PAF
is reset to HIGH on the LOW-to-HIGH transitions of the Read Clock (RCLK).
See Figure 31 and 33, Synchronous and Asynchronous Programmable
Almost-Full Flag Timng (IDT Standard and FWFT mode), for the relevant timng
information.
Each programmable almost full flag operates independently of the others.
ECHO READ CLOCK (ERCLK0/1/2/3)
There are four echo read clock outputs (two in Dual mode) available in this
device, each corresponding to their respective input read clocks in the FIFO.
The echo read clock is a free-running clock output, that will always follow the
RCLK input regardless of the read enables and read chip selects. The ERCLK
output follows the RCLK input with an associated delay. This delay provides the
user with a more effective read clock source when reading data fromthe output
bus. This is especially helpful at high speeds when variables within the device
may cause changes in the data access times. These variations in access time
may be caused by ambient temperature, supply voltage, or device characteristics.
Any variations effecting the data access time will also have a corresponding
effect on the echo read clock output produced by the FIFO, therefore the echo
read clock output level transitions should always be at the same position in time
relative to the data outputs. Note, that echo read clock is guaranteed by design
to be slower than the slowest data outputs. Refer to Figure 6,
Echo Read Clock
and Data Output Relationship
, Figures 25, 26, and 27
Echo Read Clock and
Read Enable Operation
for timng information. Each echo read clock output
operate independently of the others and transitions with respect to the data
outputs of its FIFO.
Figure 6. Echo Read Clock and Data Output Relationship
NOTES:
1.
REN
is LOW.
2. t
ERCLK
> t
A
, guaranteed by design.
3. Qslowest is the data output with the slowest access time, t
A
.
4. Time, t
D
is greater than zero, guaranteed by design.
TABLE 6 — T
SKEW
MEASUREMENT
Data Port
Configuration
DDR Input
to
DDR Output
Status Flags
T
SKEW
Measurement
Datasheet
Parameter
t
SKEW2
EF
/
OR
Negative Edge WCLK to
Positive Edge RCLK
Negative Edge RCLK to
Positive Edge WCLK
Negative Edge WCLK to
Positive Edge RCLK
Negative Edge RCLK to
Positive Edge WCLK
Negative Edge WCLK to
Positive Edge RCLK
Positive Edge RCLK to
Positive Edge WCLK
Negative Edge WCLK to
Positive Edge RCLK
Positive Edge RCLK to
Positive Edge WCLK
Positive Edge WCLK to
Positive Edge RCLK
Negative Edge RCLK to
Positive Edge WCLK
Positive Edge WCLK to
Positive Edge RCLK
Negative Edge RCLK to
Positive Edge WCLK
Positive Edge WCLK to
Positive Edge RCLK
Positive Edge RCLK to
Positive Edge WCLK
Positive Edge WCLK to
Positive Edge RCLK
Positive Edge RCLK to
Positive Edge WCLK
FF
/
IR
t
SKEW2
PAE
t
SKEW3
PAF
t
SKEW3
DDR Input
to
SDR Output
EF
/
OR
t
SKEW2
FF
/
IR
t
SKEW1
PAE
t
SKEW3
PAF
t
SKEW3
SDR Input
to
DDR Output
EF
/
OR
t
SKEW1
FF
/
IR
t
SKEW2
PAE
t
SKEW3
PAF
t
SKEW3
SDR Input
to
SDR Output
EF
/
OR
t
SKEW1
FF
/
IR
t
SKEW1
PAE
t
SKEW3
PAF
t
SKEW3
相關(guān)PDF資料
PDF描述
IDT72T54242L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54242L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T54242L5BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54242L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54242L6-7BBI 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54252L5BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54252L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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