參數(shù)資料
型號： IDT72T54252L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述： 64K X 20 OTHER FIFO, 3.6 ns, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁數(shù)： 1/56頁
文件大?。?/td> 555K
代理商： IDT72T54252L5BB
1
DSC-6158/3
MARCH 2005
IDT72T54242
IDT72T54252
IDT72T54262
2.5V QUAD/DUAL TeraSync DDR/SDR FIFO
x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
32,768 x 10 x 4/16,384 x 20 x 2
65,536 x 10 x 4/32,768 x 20 x 2
131,072 x 10 x 4/65,536 x 20 x 2
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES
Choose from among the following memory organizations:
IDT72T54242
-
32,768 x 10 x 4/32,768 x 10 x 2
IDT72T54252
-
65,536 x 10 x 4/65,536 x 10 x 2
IDT72T54262
-
131,072 x 10 x 4/131,072 x 10 x 2
User Selectable Quad / Dual Mode - Choose between two or
four independent FIFOs
Quad Mode offers
- Eight discrete clock domain, (four write clocks & four read clocks)
- Four separate write ports, write data to four independent FIFOs
- 10-bit wide write ports
- Four separate read ports, read data fromany of four independent FIFOs
- Independent set of status flags and control signals for each FIFO
Dual Mode offers
- Four discrete clock domain, (two write clocks & two read clocks)
- Two separate write ports, write data to two independent FIFOs
- 10-bit/20-bit wide write ports
- Two separate read ports, read data fromany of two independent FIFOs
- Independent set of status flags and control signals for each FIFO
- Bus-Matching on read and write port x10/x20
- Maximumdepth of each FIFO is the same as in Quad Mode
FUNCTIONAL BLOCK DIAGRAMS
Up to 200MHz operating frequency or 2Gbps throughput in SDR mode
Up to 100MHz operating frequency or 2Gbps throughput in DDR mode
Double Data Rate, DDR is selectable, providing up to 400Mbps
bandwidth per data pin
User selectable Single or Double Data Rate modes on both the
write port(s) and read port(s)
All I/Os are LVTTL/ HSTL/ eHSTL user selectable
3.3V tolerant inputs in LVTTL mode
ERCLK and
EREN
Echo outputs on all read ports
Write enable
WEN
and Chip Select
WCS
input for each write port
Read enable
REN
and Chip Select
RCS
input for each read port
User Selectable IDT Standard mode (using
EF
and
FF
) or FWFT
mode (using
IR
and
OR
)
Programmable Almost Empty and Almost Full flags per FIFO
Dedicated Serial Port for flag offset programming
Power Down pin minimizes power consumption
2.5V Supply Voltage
Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm
IEEE 1149.1 compliant JTAG port provides boundary scan function
Low Power, High Performance CMOS technology
Industrial temperature range (-40
°
C to +85
°
C)
32,768 x 10
65,536 x 10
131,072 x 10
32,768 x 10
65,536 x 10
131,072 x 10
32,768 x 10
65,536 x 10
131,072 x 10
32,768 x 10
65,536 x 10
131,072 x 10
WEN
1
WCS
1
WEN
2
WCS
2
WEN
3
WCS
3
WCLK1
WCLK2
WCLK3
D[19:10]
D[29:20]
D[39:30]
FIFO 1
FIFO 2
FIFO 3
FIFO 1
Data In
FIFO 2
Data In
FIFO 3
Data In
FF
0/
IR
0
PAF
0
FF
1/
IR
1
PAF
1
FF
2
/
IR
2
PAF
2
FF
3/
IR
3
PAF
3
W
F
WEN
0
WCS
0
D[9:0]
WCLK0
EF
0/
OR
0
PAE
0
EF
1/
OR
1
PAE
1
EF
2/
OR
2
PAE
2
EF
3/
OR
3
PAE
3
R
F
6158 drw01
Q[9:0]
RCLK1
x10
REN
0
RCS
0
OE
0
ERCLK0
RCLK0
FIFO 0
Quad Mode
FIFO 0
Data In
EREN
0
Q[19:10]
RCLK2
REN
1
RCS
1
OE
1
ERCLK1
EREN
1
Q[29:20]
RCLK3
REN
2
RCS
2
OE
2
ERCLK2
EREN
2
Q[39:30]
REN
3
RCS
3
OE
3
ERCLK3
EREN
3
FIFO 1
Data Out
FIFO 2
Data Out
FIFO 3
Data Out
FIFO 0
Data Out
x10
x10
x10
x10
x10
x10
x10
(See next page for Dual Mode)
相關(guān)PDF資料
PDF描述
IDT72T54252L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54262 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72V261LA 3.3 VOLT CMOS SuperSync FIFO
IDT72V85L15PAG 3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
IDT72V85L15PAGI 3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T54252L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54252L6-7BBI 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54262L5BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54262L5BBG 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54262L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*