參數(shù)資料
型號： IDT72T6360L7-5BBI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 13/51頁
文件大?。?/td> 0K
描述： IC FLOW-CTRL 48BIT 7-5NS 324-BGA
標(biāo)準(zhǔn)包裝： 1
類型： 連續(xù)流量控制
安裝類型： 表面貼裝
封裝/外殼： 324-BGA
供應(yīng)商設(shè)備封裝： 324-PBGA（19x19）
包裝： 托盤
其它名稱： 72T6360L7-5BBI
20
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FEBRUARY 10, 2009
ERROR DETECTION AND CORRECTION
TheErrorDetectionandCorrection(EDC)featureisavailabletoensuredata
integrity between the DDR SDRAM interface and the SFC. The EDC corrects
all single bit hard and soft errors that are accessed from the DDR SDRAM.
Multiple bit errors are not detected nor corrected.
The EDC logic blocks consist of a check bit generator and error detection
correction logic.WhentheEDCisenabled,thecheckbitgeneratorwillgenerate
8 syndrome bits on the 8-byte boundary. The 8 syndrome bits are written into
the DDR SDRAM along with the data. The SFC will burst write two cycles for
data, and one cycle for syndrome bits. In order to minimize overhead and
increasethroughput,notallmemoryintheDDRSDRAMisutilized.Table5 lists
the total usable memory for all 7 configurations when the EDC is enabled.
When a read operation is performed, the syndrome bits will be transferred
to the error detection correction logic block and decoded to determine whether
there are any single bit errors on the data. Single bit errors will be corrected
and data is passed through to the QP cache.
The EDC is enabled using the MIC[2:0] pins. When the EDC is enabled, the
dynamicsofthetotalusablememoryintheDDRSDRAMandtheSFCoperating
speed will vary, listed in Tables 6 and 7. Table 8 shows how to enable the EDC
feature for the 7 configurations
EDC Off
EDC On
Configuration 1
MIC [2:0] = 000
MIC [2:0] = 010
Configuration 2
MIC [2:0] = 001
MIC [2:0] = 011
Configuration 3
MIC [2:0] = 111
MIC [2:0] = 101
Configuration 4
MIC [2:0] = 100
MIC [2:0] = 110
Configuration 5
MIC [2:0] = 000
MIC [2:0] = 010
Configuration 6
MIC [2:0] = 100
MIC [2:0] = 110
Configuration 7
MIC [2:0] = 111
MIC [2:0] = 101
TABLE 8 – MIC[2:0] CONFIGURATIONS
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