參數(shù)資料
型號(hào): IDT72T6360L7-5BBI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 26/51頁(yè)
文件大小: 0K
描述: IC FLOW-CTRL 48BIT 7-5NS 324-BGA
標(biāo)準(zhǔn)包裝: 1
類型: 連續(xù)流量控制
安裝類型: 表面貼裝
封裝/外殼: 324-BGA
供應(yīng)商設(shè)備封裝: 324-PBGA(19x19)
包裝: 托盤
其它名稱: 72T6360L7-5BBI
32
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FEBRUARY 10, 2009
Figure 6. Master Reset and Initialization
tRSF
IDT Standard Mode
Synchronous read port selected
Synchronous write port selected
If OE = HIGH
Asynchronous read port selected
Asynchronous write port selected
2.5V I/O voltage selected
MRS
REN
WEN
SREN
SWEN
EF
OR
FF
IR
CK
Q[35:0]
FWFT
ASYR
ASYW
IOSEL
PAF
PAE
IDEM
Depth Expansion in IDT Standard Mode
Depth Expansion in FWFT Standard Mode
tRSU
tRSF
tRSU
tRSF
If OE = LOW
tPL
tRSU
3.3V I/O voltage selected
The clock may not be locked to the required operating frequency before
tPL
The clock may not be locked to the required operating frequency before
tPL
tRS
tRSF
tRH
tRSU
6357 drw20
FWFT Mode
If FWFT mode is selected
If IDT mode is selected
If FWFT mode is selected
If IDT mode is selected
NOTE:
1. For other signals that are latched during master reset, refer to Master Reset and Device Configuration section.
Symbol
Parameter
Min.
Max.
Unit
tRS
Reset Pulse Width
10
ns
tRSU
ResetSetupTime
15
ns
tRSH
Reset Hold Time
10
ns
tPL
Reset to PLL Lock
20
s
tRSF
Reset to Flag and Output
15
ns
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