參數(shù)資料
型號(hào)： IDT72T72115L5BBI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 17/53頁
文件大?。?/td> 0K
描述： IC FIFO 131072X72 5NS 324-BGA
標(biāo)準(zhǔn)包裝： 1
系列： 72T
訪問時(shí)間： 5ns
電源電壓： 2.375 V ~ 2.625 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 324-BGA
供應(yīng)商設(shè)備封裝： 324-PBGA（19x19）
包裝： 托盤
其它名稱： 72T72115L5BBI
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
OUTPUTS:
FULL FLAG (
FF/IR )
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (
FF) function
is selected. When the FIFO is full,
FF will go LOW, inhibiting further write
operations. When
FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRS or PRS), FF will go LOW after D writes to the FIFO
(D =16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the
IDT72T72105 and 131,072 for the IDT72T72115). See Figure 11, Write Cycle
and Full Flag Timing (IDT Standard Mode), for the relevant timing information.
In FWFT mode, the Input Ready (
IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
anyfreespaceleft,
IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
are performed after a reset (either
MRSorPRS),IRwillgoHIGHafterD writes
to the FIFO (D =16,385 for the IDT72T7285, 32,769 for the IDT72T7295,
65,537 for the IDT72T72105 and 131,073 for the IDT72T72115). See Figure
14, Write Timing (FWFT Mode), for the relevant timing information.
The
IRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IRisonegreaterthanneededto
assert
FF in IDT Standard mode.
FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare
double register-buffered outputs.
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
write pointer to the ‘marked’ location. This differs from normal mode where this
flag is a comparison of the write pointer to the read pointer.
EMPTY FLAG (
EF/OR )
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF)
functionisselected. WhentheFIFOisempty,
EFwillgoLOW,inhibitingfurther
readoperations. When
EFisHIGH,theFIFOisnotempty.SeeFigure12,Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
therelevanttiminginformation.
InFWFTmode,theOutputReady(
OR)functionisselected.ORgoesLOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs.
ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
the last word from the FIFO memory to the outputs.
OR goes HIGH only with
a true read (RCLK with
REN = LOW). The previous data stays at the outputs,
indicatingthelastwordwasread. Furtherdatareadsareinhibiteduntil
ORgoes
LOW again. See Figure 15, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In FWFT
mode,
OR isatripleregister-bufferedoutput.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF)
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS), PAFwillgoLOWafter(D - m)wordsarewritten
to the FIFO. The
PAFwillgoLOWafter(16,384-m)writesfortheIDT72T7285,
(32,768-m)writesfortheIDT72T7295,(65,536-m)writesfortheIDT72T72105
and (131,072-m) writes for the IDT72T72115. The offset “m” is the full offset
value. The default setting for this value is stated in the footnote of Table 3.
In FWFT mode, the
PAF will go LOW after (16,385-m) writes for the
IDT72T7285, (32,769-m) writes for the IDT72T7295, (65,537-m) writes for the
IDT72T72105 and (131,073-m) writes for the IDT72T72115, where m is the
full offset value. The default setting for this value is stated in Table 4.
See Figure 23, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
If asynchronous
PAF configurationisselected,the PAF isassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).
PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). Ifsynchronous
PAF
configuration is selected, the
PAFisupdatedontherisingedgeofWCLK. See
Figure 25, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT
Mode).
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
write pointer to the ‘marked’ location. This differs from normal mode where this
flag is a comparison of the write pointer to the read pointer.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE)
The Programmable Almost-Empty flag (
PAE)willgoLOWwhentheFIFO
reaches the almost-empty condition. In IDT Standard mode,
PAEwillgoLOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 24, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
If asynchronous
PAEconfigurationisselected,the PAEisassertedLOW
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).
PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). Ifsynchronous
PAE
configuration is selected, the
PAEisupdatedontherisingedgeofRCLK. See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode).
HALF-FULL FLAG (
HF )
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyondhalf-fullsets
HFLOW.TheflagremainsLOWuntilthedifferencebetween
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets
HF
HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset(
MRSorPRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 16,384 for the
IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and
131,072 for the IDT72T72115.
In FWFT mode, if no reads are performed after reset (
MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 16,385 for the
IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and
131,073 for the IDT72T72115.
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because
HFisupdatedbybothRCLKand
WCLK, it is considered asynchronous.
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