IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18" />
參數(shù)資料
型號(hào): IDT72V205L20TF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 12/25頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC 16KX9 20NS 64QFP
標(biāo)準(zhǔn)包裝: 80
系列: 72V
功能: 異步
存儲(chǔ)容量: 144K(16K x 9)
訪問(wèn)時(shí)間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 72V205L20TF
2
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH 2013
PIN CONFIGURATIONS
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
DESCRIPTION (CONTINUED)
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D
16
D
17
GND
RCLK
REN
LD
OE
RS
V
CC
GND
EF
Q
17
Q
16
GND
Q
15
V
CC
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PAE
FL
WCLK
WEN
WXI V
CC
PAF
RXI
FF
WXO
/HF
RXO
Q
0
Q
1
GND
Q
2
Q
3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
4294 drw 02
ThesynchronousFIFOshavetwofixedflags,EmptyFlag/OutputReady
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
programmableflagsiscontrolledbyasimplestatemachine,andisinitiatedby
asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO
is used in a single device configuration.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall-Through (FWFT) mode.
InIDTStandardMode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
tothedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoes
not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or
FirstWordFallThroughmode(FWFT).TheXIandXOpinsareusedtoexpand
the FIFOs. In depth expansion configuration, First Load (FL) is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using
high-speedsubmicronCMOStechnology.
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