IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
參數(shù)資料
型號: IDT72V223L7-5PF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/45頁
文件大?。?/td> 0K
描述: IC FIFO 512X18 7-5NS 80QFP
標準包裝: 5
系列: 72V
功能: 異步,同步
存儲容量: 9.2K(512 x 18)
數(shù)據(jù)速率: 133MHz
訪問時間: 5ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應商設備封裝: 80-TQFP(14x14)
包裝: 托盤
其它名稱: 72V223L7-5PF
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
DESCRIPTION:
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO)
memories with clocked read and write controls and a flexible Bus-Matching x9/
x18 data flow. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:
Flexible x9/x18 Bus-Matching on both read and write ports
The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.
The period required by the retransmit operation is now fixed and short.
The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
Asynchronous/Synchronous translation on the read or write ports
High density offerings up to 1 Mbit
Bus-Matching SuperSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
PIN CONFIGURATIONS
TQFP (PN80-1, order code: PF)
TOP VIEW
DNC(1)
OE
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
IW
GND
D17
D16
D14
D15
D13
GND
D12
D11
D10
D9
D8
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
60
59
RT
Q17
Q16
GND
Q15
Q14
Q13
Q12
Q11
GND
Q9
Q8
Q7
INDEX
WEN
SEN
DNC(1)
Q10
VCC
4666 drw02
20
1
VCC
VCC
GND
VCC
VCC
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
80
79
WCLK
PRS
MRS
LD
FWFT/SI
FF
/IR
PAF
OW
FSEL0
HF
FSEL1
BE
IP
V
CC
PAE
PFM
EF
/OR
RM
RCLK
REN
D7
D6
GND
D5
D4
D3
D2
D1
D0
GND
Q0
Q1
GND
Q2
Q3
V
CC
Q4
Q5
GND
Q6
NOTE:
1. DNC = Do Not Connect.
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