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參數資料
| 型號： | IDT72V255LA15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 21/27頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO SS 8192X18 15NS 64-TQFP |
| 標準包裝： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 144K（8K x 18） |
| 訪問時間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V255LA15PF8 |
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IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
DESCRIPTION (CONTINUED)
Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72V255LA
72V265LA
PARTIAL RESET (PRS)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (RT)
4672 drw 03
HALF FULL FLAG (HF)
SERIAL ENABLE(SEN)
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode, thefirstwordwrittentoanemptyFIFOwillnotappear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
RENandenablingarisingRCLKedge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
RENdoes
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on
REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and
PAF (Programmable Almost-Full flag). The EF and
FF functions are selected in IDT Standard mode. The IR and OR functions
are selected in FWFT mode.
HF, PAE and PAFare always available for use,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point in
memory. (See Table I and Table II.) Programmable offsets determine the flag
switching threshold and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, so that
PAEcanbesettoswitchat127
or 1,023 locations from the empty boundary and the
PAFthresholdcanbeset
at 127 or 1,023 locations from the full boundary. These choices are made with
the
LD pin during Master Reset.
For serial programming,
SEN together with LD on each rising edge of
WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,
WENtogetherwithLDoneachrisingedgeofWCLK,areused
to load the offset registers via Dn.
REN together with LD on each rising edge
of RCLK can be used to read the offsets in parallel from Qn regardless of
whether serial or parallel offset loading has been selected.
During Master Reset (
MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The
LDpinselectseitherapartialflagdefault
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023
with serial programming. The flags are updated according to the timing mode
and default offsets selected.
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag programming
method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect.
PRS is useful for resetting a device in mid-operation, when
reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the
RTinputduringarisingRCLKedgeinitiatesaretransmit
operation by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT72V255LA/72V265LA are fabricated using IDT’s high speed
submicron CMOS technology.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT72V255LA15PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X18 15NS 64TQFP |
| IDT72V255LA15PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X18 15NS 64TQFP |
| IDT72V255LA15PFI | 功能描述:IC FIFO SS 8192X18 15NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V255LA15PFI8 | 功能描述:IC FIFO SS 8192X18 15NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V255LA15TF | 功能描述:IC FIFO SS 8192X18 15NS 64-STQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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