參數(shù)資料
型號(hào): IDT72V255LA15PFI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 24/27頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SS 8192X18 15NS 64-TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 同步
存儲(chǔ)容量: 144K(8K x 18)
訪問(wèn)時(shí)間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱(chēng): 72V255LA15PFI8
6
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
4672 drw 04
330
30pF*
510
3.3V
D.U.T.
* Includes jig and scope capacitances.
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC 3.3V
± 0.3V,TA = -40°C to +85°C)
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 2
AC TEST CONDITIONS
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 15ns speed grade is available as a standard device.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
IDT72V255LA10
IDT72V255LA15
IDT72V255LA20
IDT72V265LA10
IDT72V265LA15
IDT72V265LA20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
100
66.7
50
M H z
tA
Data Access Time
2
6.5
2
10
2
12
ns
tCLK
Clock Cycle Time
10
15
20
ns
tCLKH
Clock High Time
4.5
6
8
ns
tCLKL
Clock Low Time
4.5
6
8
ns
tDS
Data Setup Time
3
4
5
ns
tDH
Data Hold Time
0.5
1
1
ns
tENS
Enable Setup Time
3
4
5
ns
tENH
Enable Hold Time
0.5
1
1
ns
tLDS
Load Setup Time
3
4
5
ns
tLDH
Load Hold Time
0.5
1
1
ns
tRS
Reset Pulse Width(3)
10
15
20
ns
tRSS
Reset Setup Time
10
15
20
ns
tRSR
Reset Recovery Time
10
15
20
ns
tRSF
Reset to Flag and Output Time
10
15
20
ns
tFWFT
Mode Select Time
0
0
0
ns
tRTS
Retransmit Setup Time
3
4
5
ns
tOLZ
Output Enable to Output in Low Z(4)
0—
0
0—
ns
tOE
Output Enable to Output Valid
2
6
3
8
3
10
ns
tOHZ
Output Enable to Output in High Z(4)
26
3
8
3
10
ns
tWFF
Write Clock to
FF or IR
6.5
10
12
ns
tREF
Read Clock to
EF or OR
6.5
10
12
ns
tPAF
Write Clock to
PAF
6.5
10
12
ns
tPAE
Read Clock to
PAE
6.5
10
12
ns
tHF
Clock to
HF
—16
20
22
ns
tSKEW1
Skew time between RCLK and WCLK for
FF/IR
5—
6
10
ns
tSKEW2
Skew time between RCLK and WCLK for
PAE and PAF
12
15
20
ns
tSKEW3
Skew time between RCLK and WCLK for
EF/OR
60
60
60
ns
tSKEW4
Skew time between RCLK and WCLK for
PAE and PAF
15
17
25
ns
for Re-transmit operation
Figure 2. Output Load
Commercial
Com’l & Ind’l(2)
Commercial
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