IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
參數(shù)資料
型號(hào)： IDT72V263L10PFI8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 14/45頁(yè)
文件大?。?/td> 0K
描述： IC FIFO 8192X18 10NS 80QFP
標(biāo)準(zhǔn)包裝： 750
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 144K（8K x 18）
數(shù)據(jù)速率： 100MHz
訪問(wèn)時(shí)間： 10ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 72V263L10PFI8
21
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
BUS-MATCHING (IW, OW)
The pins IW and OW are used to define the input and output bus widths.
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
sizes. See Table 1 for control settings. All flags will operate based on the word/
byte size boundary as defined by the selection of the widest input or output bus
width.
BIG-ENDIAN/LITTLE-ENDIAN (
BE)
DuringMasterReset,aLOWon
BEwillselectBig-Endianoperation.AHIGH
on
BEduringMasterResetwillselectLittle-Endianformat.Thisfunctionisuseful
when data is written into the FIFO in word format (x18) and read out of the FIFO
in word format (x18) or byte format (x9). If Big-Endian mode is selected, then
the most significant byte of the word written into the FIFO will be read out of the
FIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformatisselected,
then the least significant byte of the word written into the FIFO will be read out
first,followedbythemostsignificantbyte.Themodedesiredisconfiguredduring
master reset by the state of the Big-Endian (
BE) pin. Refer to Figure 4, Bus-
Matching Byte Arrangement, for a diagram showing the byte arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset During Master Reset, a LOW on PFM will select
Asynchronous Programmable flag timing mode. A HIGH on PFM will select
Synchronous Programmable flag timing mode. If asynchronous
PAF/PAE
configuration is selected (PFM, LOW during
MRS),thePAEisassertedLOW
on the LOW-to-HIGH transition of RCLK.
PAEisresettoHIGHontheLOW-to-
HIGH transition of WCLK. Similarly, the
PAFisassertedLOWontheLOW-to-
HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous
PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the
PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly,
PAFisassertedandupdatedontherisingedgeofWCLK
only and not RCLK. The mode desired is configured during master reset by the
state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.
AHIGHwillselectInterspersedParitymode.TheIPbitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit position D8 and D17 during
the parallel programming of the flag offsets, and will therefore ignore D8 when
loading the offset register in parallel mode. This is also applied to the output
register when reading the value of the offset register. If Interspersed Parity is
selected then output Q8 will be invalid. If Non-Interspersed Parity mode is
selected, then D16 and D17 are the parity bits and are ignored during parallel
programmingoftheoffsets.(D8becomesavalidbit).Additionally,outputQ8will
become a valid bit when performing a read of the offset register. IP mode is
selectedduringMasterResetbythestateoftheIPinputpin. InterspersedParity
control only has an effect during parallel programming of the offset registers. It
does not effect the data written to and read from the FIFO.
OUTPUTS:
FULL FLAG (
FF/IR)
Thisisadualpurposepin.InIDTStandardmode,theFullFlag(
FF)function
is selected. When the FIFO is full,
FF will go LOW, inhibiting further write
operations. When
FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRS or PRS), FF will go LOW after D writes to the FIFO.
If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223,
1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253,
8,192fortheIDT72V263,16,384fortheIDT72V273,32,768fortheIDT72V283
and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are
selected,D = 1,024fortheIDT72V223,2,048fortheIDT72V233,4,096forthe
IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for
the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293.
See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the
relevanttiminginformation.
In FWFT mode, the Input Ready (
IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
anyfreespaceleft,
IRgoesHIGH,inhibitingfurtherwriteoperations.Ifnoreads
are performed after a reset (either
MRSorPRS),IRwillgoHIGHafterD writes
to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 513 for the
IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the
IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for
the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output
bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the
IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for
the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and
131,073 for the IDT72V293. See Figure 9, Write Timing (FWFT Mode), for
therelevanttiminginformation.
The
IRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IRisonegreaterthanneededto
assert
FF in IDT Standard mode.
FF/IRissynchronousandupdatedontherisingedgeofWCLK. FF/IRare
double register-buffered outputs.
EMPTY FLAG (
EF/OR)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF)
function is selected. When the FIFO is empty,
EFwillgoLOW,inhibitingfurther
read operations. When
EFisHIGH,theFIFOisnotempty.SeeFigure8,Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
therelevanttiminginformation.
InFWFTmode,theOutputReady(
OR)functionisselected.ORgoesLOW
at the same time that the first word written to an empty FIFO appears valid on
theoutputs.
ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshiftsthe
last word from the FIFO memory to the outputs.
ORgoesHIGHonlywithatrue
read(RCLKwith
REN=LOW).Thepreviousdatastaysattheoutputs,indicating
the last word was read. Further data reads are inhibited until
OR goes LOW
again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In FWFT
mode,
OR isatripleregister-bufferedoutput.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF)
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS), PAF will go LOW after (D-m) words are written
to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (512-m)
writes for the IDT72V223, (1,024-m) writes for the IDT72V233, (2,048-m)
writes for the IDT72V243, (4,096-m) writes for the IDT72V253, (8,192-m)
writes for the IDT72V263, (16,384-m) writes for the IDT72V273, (32,768-m)
writes for the IDT72V283 and (65,536-m) writes for the IDT72V293. If both x9
Input and x9 Output bus Widths are selected, (D-m) = (1,024-m) writes for the
IDT72V223, (2,048-m) writes for the IDT72V233, (4,096-m) writes for the
IDT72V243, (8,192-m) writes for the IDT72V253, (16,384-m) writes for the
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