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參數(shù)資料
| 型號： | IDT72V263L10PFI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 9/45頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 8192X18 10NS 80QFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲容量： | 144K（8K x 18） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時間： | 10ns |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V263L10PFI8 |
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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programmingof
PAEandPAFvaluescanbeachievedbyusingacombination
ofthe
LD,SEN,WCLKandSIinputpins.ProgrammingPAEandPAFproceeds
as follows: when
LD and SEN are set LOW, data on the SI input are written,
onebitforeachWCLKrisingedge,startingwiththeEmptyOffsetLSBandending
with the Full Offset MSB. If x9 to x9 mode is selected, a total of 20 bits for the
IDT72V223, 22 bits for the IDT72V233, 24 bits for the IDT72V243, 26 bits for
the IDT72V253, 28 bits for the IDT72V263, 30 bits for the IDT72V273, 32 bits
for the IDT72V283 and 34 bits for the IDT72V293. For any other mode of
operation (that includes x18 bus width on either the Input or Output), minus 2
bits from the values above. So, a total of 18 bits for the IDT72V223, 20 bits for
the IDT72V233, 22 bits for the IDT72V243, 24 bits for the IDT72V253, 26 bits
for the IDT72V263, 28 bits for the IDT72V273, 30 bits for the IDT72V283 and
32 bits for the IDT72V293. See Figure 15, Serial Loading of Programmable
Flag Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively.
PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programmingsequence.Inthiscase,theprogrammingofalloffsetbitsdoesnot
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing
LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling
WEN. When WEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruptionofserialprogrammingisdesired,itissufficienteithertoset
LDLOW
and deactivate
SENortosetSENLOWanddeactivateLD.OnceLDandSEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written.MeasuringfromtherisingWCLKedgethatachievestheabovecriteria;
PAFwillbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalid
after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
PARALLEL PROGRAMMING MODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programmingof
PAEandPAFvaluescanbeachievedbyusingacombination
of the
LD,WCLK,WENandDninputpins.IftheFIFOisconfiguredforaninput
bus width and output bus width both set to x9, then the total number of write
operations required to program the offset registers is 4 for the IDT72V223/
72V233/72V243/72V253/72V263/72V273/72V283 or 6 for the IDT72V293.
Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a
detailed diagram of the data input lines D0-Dn used during parallel program-
ming. If the FIFO is configured for an input to output bus width of x9 to x18, x18
to x9 or x18 to x18, then the following number of write operations are required.
For an input bus width of x18 a total of 2 write operations will be required to
program the offset registers for the IDT72V223/72V233/72V243/72V253/
72V263/72V273/72V283/72V293.Foraninputbuswidthofx9atotalof4write
operations will be required to program the offset registers for the IDT72V223/
72V233/72V243/72V253/72V263/72V273/72V283/72V293. Refer to Figure
3,ProgrammableFlagOffsetProgrammingSequence,foradetaileddiagram.
For example, programming
PAE and PAF on the IDT72V293 configured
for x18 bus width proceeds as follows: when
LD and WEN are set LOW, data
ontheinputsDnarewrittenintotheLSBoftheEmptyOffsetRegisteronthefirst
LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition
ofWCLK,dataarewrittenintotheMSBoftheEmptyOffsetRegister.Onthethird
LOW-to-HIGHtransitionofWCLK,dataarewrittenintotheLSBoftheFullOffset
Register.OnthefourthLOW-to-HIGHtransitionofWCLK,dataarewritteninto
theMSBoftheFullOffsetRegister.ThefifthLOW-to-HIGHtransitionofWCLK,
data are written, once again to the Empty Offset Register. Note that for x9 bus
width, one extra Write cycle is required for both the Empty Offset Register and
Full Offset Register. See Figure 16, Parallel Loading of Programmable Flag
Registers, for the timing diagram for this mode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
shouldnotbeperformedsimultaneouslytotheoffsetregisters.AMasterReset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers. Refer to Figure 3, Programmable
Flag Offset Programming Sequence, for a detailed diagram of the data input
lines D0-Dn used during parallel programming.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing
LD HIGH, write operations can be redirected to
theFIFOmemory.When
LDissetLOWagain,andWENisLOW,thenextoffset
register in sequence is written to. As an alternative to holding
WENLOWand
toggling
LD,parallelprogrammingcanalsobeinterruptedbysettingLDLOW
and toggling
WEN.
Note that the status of a programmable flag (
PAEorPAF)outputisinvalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria;
PAFwillbevalidafter
twomorerisingWCLKedgesplustPAF,
PAEwillbevalidafterthenexttworising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when
LDissetLOWandRENissetLOW.IftheFIFOisconfiguredforan
inputbuswidthandoutputbuswidthbothsettox9,thenthetotalnumberofread
operationsrequiredtoreadtheoffsetregistersis4fortheIDT72V223/72V233/
72V243/72V253/72V263/72V273/72V283 or 6 for the IDT72V293. Refer to
Figure 3, Programmable Flag Offset Programming Sequence, for a detailed
diagram of the data input lines D0-Dn used during parallel programming. If the
FIFO is configured for an input to output bus width of x9 to x18, x18 to x9 or
x18 to x18, then the following number of read operations are required: for an
output bus width of x18 a total of 2 read operations will be required to read the
offsetregistersfortheIDT72V223/72V233/72V243/72V253/72V263/72V273/
72V283/72V293. For an output bus width of x9 a total of 4 read operations will
be required to read the offset registers for the IDT72V223/72V233/72V243/
72V253/72V263/72V273/72V283/72V293. Refer to Figure 3, Program-
mable Flag Offset Programming Sequence, for a detailed diagram. For
example, reading
PAE and PAF on the IDT72V293 configured for x18 bus
widthproceedsasfollows:dataarereadviaQn fromtheEmptyOffsetRegister
on the first and second LOW-to-HIGH transition of RCLK. Upon the third and
fourth LOW-to-HIGH transition of RCLK, data are read from the Full Offset
Register. The fifth and sixth transition of RCLK reads, once again, from the
Empty Offset Register. Note that for a x9 bus width, one extra Read cycle is
requiredforboththeEmptyOffsetRegisterandFullOffsetRegister.SeeFigure
17, Parallel Read of Programmable Flag Registers, for the timing diagram for
thismode.
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| IDT72V263L15PF | 功能描述:IC FIFO 8192X18 15NS 80QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V263L15PF8 | 功能描述:IC FIFO 8192X18 15NS 80QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V263L6BC | 功能描述:IC FIFO 8192X18 16NS 100LBGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V263L6BCG | 功能描述:IC FIFO 8192X9 SYNC 6NS 100BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V263L6BCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 3.3V SUPERSYNC II 100BGA |
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