IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
參數資料
型號： IDT72V263L7-5PF8
廠商： IDT, Integrated Device Technology Inc
文件頁數： 4/45頁
文件大?。?/td> 0K
描述： IC FIFO 8192X18 7-5NS 80QFP
標準包裝： 750
系列： 72V
功能： 異步，同步
存儲容量： 144K（8K x 18）
數據速率： 133MHz
訪問時間： 5ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應商設備封裝： 80-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 72V263L7-5PF8
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 support two different timing modes of operation: IDT Standard mode
or First Word Fall Through (FWFT) mode. The selection of which mode will
operate is determined during Master Reset, by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (
EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(
FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR)toindicatewhetherornotthere
is valid data at the data outputs (Qn). It also uses Input Ready (
IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,
REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (
REN) and RCLK.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags,
FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (
WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (
EF)willgoHIGH.Subsequentwriteswillcontinue
to fill up the FIFO. The Programmable Almost-Empty flag (
PAE)willgoHIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(
HF)wouldtoggletoLOWonce
(D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width
is selected, (D/2 + 1) = the 257th word for the IDT72V223, 513rd word for
IDT72V233,1,025thwordfortheIDT72V243,2,049thwordfortheIDT72V253,
4,097th word for the IDT72V263, 8,193th word for IDT72V273, 16,385th word
for the IDT72V283 and 32,769th word for the IDT72V293. If both x9 Input and
x9 Output bus Widths are selected, (D/2 + 1) = the 513rd word for the
IDT72V223, 1,025th word for IDT72V233, 2,049th word for the IDT72V243,
4,097th word for the IDT72V253, 8,193rd word for the IDT72V263, 16,385th
word for IDT72V273, 32,769th word for the IDT72V283 and 65,537th word
for the IDT72V293. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (
PAF) to go LOW. Again, if no reads are
performed, the
PAFwillgoLOWafter(D-m)writestotheFIFO.Ifx18Inputor
x18 Output bus Width is selected, (D-m) = (512-m) writes for the IDT72V223,
(1,024-m) writes for the IDT72V233, (2,048-m) writes for the IDT72V243 and
(4,096-m) writes for the IDT72V253, (8,192-m) writes for the IDT72V263,
(16,384-m) writes for the IDT72V273, (32,768-m) writes for the IDT72V283
and (65,536-m) writes for the IDT72V293. If both x9 Input and x9 Output bus
Widths are selected, (D-m) = (1,024-m) writes for the IDT72V223, (2,048-m)
writes for the IDT72V233, (4,096-m) writes for the IDT72V243, (8,192-m)
writes for the IDT72V253, (16,384-m) writes for the IDT72V263, (32,768-m)
writesfortheIDT72V273,(65,536-m)writesfortheIDT72V283and(131,072-m)
writesfortheIDT72V293.Theoffset“m”isthefulloffsetvalue.Thedefaultsetting
forthesevaluesarestatedinthefootnoteofTable2.Thisparameterisalsouser
programmable. See section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (
FF)willgoLOW,inhibitingfurtherwrite
operations.Ifnoreadsareperformedafterareset,
FFwillgoLOWafterDwrites
to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 512 writes
for the IDT72V223, 1,024 writes for the IDT72V233, 2,048 writes for the
IDT72V243, 4,096 writes for the IDT72V253, 8,192 writes for the IDT72V263,
16,384 writes for the IDT72V273, 32,768 writes for the IDT72V283 and 65,536
writesfortheIDT72V293.Ifbothx9Inputandx9OutputbusWidthsareselected,
D = 1024 writes for the IDT72V223, 2,048 writes for the IDT72V233, 4,096
writes for the IDT72V243, 8,192 writes for the IDT72V253, 16,384 writes for
the IDT72V263, 32,768 writes for the IDT72V273, 65,536 writes for the
IDT72V283 and 131,072 writes for the IDT72V293, respectively.
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequentreadoperationswillcause
PAFandHFtogoHIGHattheconditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
When the last word has been read from the FIFO, the
EFwillgoLOWinhibiting
further read operations.
REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the
EFandFFoutputsaredouble
register-bufferedoutputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags,
IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into the FIFO,
WEN must be LOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitions of WCLK. After the first write is performed, the Output Ready (
OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO.
PAEwillgo
HIGH after n+2 words have been loaded into the FIFO, where n is the empty
offsetvalue.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the
HF would toggle to LOW once the (D/2 + 2)
wordswerewrittenintotheFIFO.Ifx18Inputorx18OutputbusWidthisselected,
(D/2 + 2) = the 258th word for the IDT72V223, 514th word for IDT72V233,
1,026th word for the IDT72V243, 2,050th word for the IDT72V253, 4,098th
word for the IDT72V263, 8,194th word for IDT72V273, 16,386th word for the
IDT72V283 and 32,770th word for the IDT72V293. If both x9 Input and x9
OutputbusWidthsareselected,(D/2 + 2) = the514thwordfortheIDT72V223,
1,026th word for IDT72V233, 2,050th word for the IDT72V243, 4,098th word
for the IDT72V253, 8,194th word for the IDT72V263, 16,386th word for
IDT72V273, 32,770th word for the IDT72V283 and 65,538th word for the
IDT72V293.ContinuingtowritedataintotheFIFOwillcausethe
PAFtogoLOW.
Again, if no reads are performed, the
PAFwillgoLOWafter(D-m)writestothe
FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (513-m) writes
for the IDT72V223, (1,025-m) writes for the IDT72V233, (2,049-m) writes for
the IDT72V243, (4,097-m) writes for the IDT72V253, (8,193-m) writes for the
IDT72V263, (16,385-m) writes for the IDT72V273, (32,769-m) writes for the
IDT72V283 and (65,537-m) writes for the IDT72V293. If both x9 Input and x9
Output bus Widths are selected, (D-m) = (1,025-m) writes for the IDT72V223,
(2,049-m) writes for the IDT72V233, (4,097-m) writes for the IDT72V243,
(8,193-m) writes for the IDT72V253, (16,385-m) writes for the IDT72V263,
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參數描述
IDT72V263L7-5PFI 功能描述:IC FIFO 8192X18 7-5NS 80QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V265LA10PF 功能描述:IC FIFO SS 16384X18 10NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V265LA10PF8 功能描述:IC FIFO SS 16384X18 10NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V265LA10PFG 功能描述:IC FIFO SS 16384X18 10NS 64-TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數據速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應商設備封裝:120-HLQFP（14x14） 包裝:托盤 產品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984
IDT72V265LA10PFG8 功能描述:IC FIFO SS 16384X18 10NS 64-TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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