IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� IDT72V273L15PF
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 23/45闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO 16384X18 15NS 80QFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 45
绯诲垪锛� 72V
鍔熻兘锛� 鍚屾
瀛樺劜(ch菙)瀹归噺锛� 288K锛�16K x 18锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 166MHz
瑷晱(w猫n)鏅�(sh铆)闁擄細 15ns
闆绘簮闆诲锛� 3.15 V ~ 3.45 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 80-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 80-TQFP锛�14x14锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 72V273L15PF
3
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
PIN CONFIGURATIONS (CONTINUED)
BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC)
TOP VIEW
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either an 18-bit or a 9-bit width as determined by the state
ofexternalcontrolpinsInputWidth(IW)andOutputWidth(OW)duringtheMaster
Reset cycle.
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the input port is
controlledbyaWriteClock(WCLK)inputandaWriteEnable(
WEN)input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when
WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the
WEN input should be tied to its active state, (LOW).
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (
REN)input. Data
is read from the FIFO on every rising edge of RCLK when
REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the
REN input should be tied to its
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport
the FIFO must be configured for Standard IDT mode, and the
OE input used
to provide three-state control of the outputs, Qn.
The frequencies of both the RCLK and the WCLK signals may vary from 0
tofMAXwithcompleteindependence.Therearenorestrictionsonthefrequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
RENandenablingarisingRCLKedge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
RENdoes
DESCRIPTION (CONTINUED)
ASYW
WEN
WCLK
PAF
FF/IR
BE
ASYR
PFM
RM
REN
SEN
MRS
PRS
LD
HF
FSEL0
IP
PAE
EF/OR
RCLK
FWFT/SI
OW
VCC
RT
OE
D17
IW
VCC
GND
VCC
Q16
Q17
D16
D13
VCC
GND
Q15
D15
D14
VCC
GND
Q12
D11
D12
VCC
GND
Q10
D8
D9
D10
VCC
Q8
D6
D7
D2
D0
Q7
D5
D4
D3
D1
TRST
TDI
Q0
Q3
Q5
Q6
A1 BALL PAD CORNER
A
B
C
D
E
F
G
H
J
K
12
3
4
5
6
7
8
9
10
4666 drw02b
GND
VCC
Q14
GND
VCC
Q13
Q9
GND
VCC
Q11
TMS
TCK
TDO
Q2
Q4
VCC
Q1
VCC
FSEL1
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
IDT72V273L15PF8 鍔熻兘鎻忚堪:IC FIFO 16384X18 15NS 80QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜(ch菙)瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱(w猫n)鏅�(sh铆)闁�:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V273L6BC 鍔熻兘鎻忚堪:IC FIFO 16384X18 6NS 100BGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:15 绯诲垪:74F 鍔熻兘:鐣版 瀛樺劜(ch菙)瀹归噺:256锛�64 x 4锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱(w猫n)鏅�(sh铆)闁�:- 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:閫氬瓟 灏佽/澶栨:24-DIP锛�0.300"锛�7.62mm锛� 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-PDIP 鍖呰:绠′欢 鍏跺畠鍚嶇ū:74F433
IDT72V273L6PF 鍔熻兘鎻忚堪:IC FIFO 16384X18 6NS 80QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:15 绯诲垪:74F 鍔熻兘:鐣版 瀛樺劜(ch菙)瀹归噺:256锛�64 x 4锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱(w猫n)鏅�(sh铆)闁�:- 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:閫氬瓟 灏佽/澶栨:24-DIP锛�0.300"锛�7.62mm锛� 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-PDIP 鍖呰:绠′欢 鍏跺畠鍚嶇ū:74F433
IDT72V273L6PF8 鍔熻兘鎻忚堪:IC FIFO 16384X18 6NS 80QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜(ch菙)瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱(w猫n)鏅�(sh铆)闁�:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
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娣诲姞鏇村閲囪臣(g貌u)

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