IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72V273L15PF
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 36/45闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO 16384X18 15NS 80QFP
妯欐簴鍖呰锛� 45
绯诲垪锛� 72V
鍔熻兘锛� 鍚屾
瀛樺劜瀹归噺锛� 288K锛�16K x 18锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 166MHz
瑷晱鏅傞枔锛� 15ns
闆绘簮闆诲锛� 3.15 V ~ 3.45 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 80-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 80-TQFP锛�14x14锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 72V273L15PF
41
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
Figure 31. Standard JTAG Timing
SYSTEM INTERFACE PARAMETERS
Parameter
Symbol
Test
Conditions
Min.
Max. Units
JTAG Clock Input Period tTCK
-
100
-
ns
JTAG Clock HIGH
tTCKHIGH
-40
-
ns
JTAG Clock Low
tTCKLOW
-40
-
ns
JTAG Clock Rise Time
tTCKRise
--
5(1)
ns
JTAG Clock Fall Time
tTCKFall
--
5(1)
ns
JTAG Reset
tRST
-50
-
ns
JTAG Reset Recovery
tRSR
-50
-
ns
JTAG AC ELECTRICAL
CHARACTERISTICS
(VCC = 3.3V
卤 5%; Tcase = 0掳C to +85掳C)
NOTE:
1. 50pf loading on external output signals.
NOTE:
1. Guaranteed by design.
tTCK
t4
t2
t3
t1
tDS
tDH
TDO
TDI/
TMS
TCK
TRST
t5
tDO
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t3 = tTCKFALL
t4 = tTCKRise
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
4666 drw34
t6
IDT72V223
IDT72V233
IDT72V243
IDT72V253
IDT72V263
IDT72V273
IDT72V283
IDT72V293
Parameter
Symbol
Test Conditions
Min.
Max.
Units
DataOutput
tDO = Max
-
20
ns
Data Output Hold
tDOH(1)
0-
ns
Data Input
tDS
trise=3ns
10
-
ns
tDH
tfall=3ns
10
-
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
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IDT72V273L6BC 鍔熻兘鎻忚堪:IC FIFO 16384X18 6NS 100BGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:15 绯诲垪:74F 鍔熻兘:鐣版 瀛樺劜瀹归噺:256锛�64 x 4锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱鏅傞枔:- 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:閫氬瓟 灏佽/澶栨:24-DIP锛�0.300"锛�7.62mm锛� 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-PDIP 鍖呰:绠′欢 鍏跺畠鍚嶇ū:74F433
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IDT72V273L6PF8 鍔熻兘鎻忚堪:IC FIFO 16384X18 6NS 80QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72V273L6PFG 鍔熻兘鎻忚堪:IC FIFO 16384X18 6NS 80QFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯欐簴鍖呰:15 绯诲垪:74F 鍔熻兘:鐣版 瀛樺劜瀹归噺:256锛�64 x 4锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱鏅傞枔:- 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:閫氬瓟 灏佽/澶栨:24-DIP锛�0.300"锛�7.62mm锛� 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-PDIP 鍖呰:绠′欢 鍏跺畠鍚嶇ū:74F433
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娣诲姞鏇村閲囪臣

鎴戠殑鑱�(li谩n)绯绘柟寮�

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