參數(shù)資料
型號(hào): IDT72V3613L20PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/25頁
文件大?。?/td> 0K
描述: IC FIFO CLOCK 64X36 20NS 120TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 同步
存儲(chǔ)容量: 2.3K(64 x 36)
數(shù)據(jù)速率: 50MHz
訪問時(shí)間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V3613L20PF8
3.3 VOLT CMOS CLOCKED FIFO WITH
BUS-MATCHINGANDBYTESWAPPING
64 x 36
IDT72V3613
1
JANUARY 2014
2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4661/5
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEATURES:
64 x 36 storage capacity FIFO buffering data from Port A to Port B
Supports clock frequencies up to 67MHz
Fast access times of 10ns
Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of data on
a single clock edge)
Mailbox bypass registers in each direction
Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)
Selection of Big- or Little-Endian format for word and byte bus
sizes
Three modes of byte-order swapping on Port B
Programmable Almost-Full and Almost-Empty flags
Microprocessor interface control logic
FF , AF flags synchronized by CLKA
EF , AE flags synchronized by CLKB
Passive parity checking on each Port
Parity Generation can be selected for each Port
Available in space saving 120-pin thin quad flat package (TQFP)
Green parts available, see ordering information
DESCRIPTION:
TheIDT72V3613isdesignedtorunoffa3.3Vsupplyforexceptionallylow-
power consumption. This device is a monolithic, high-speed, low-power,
CMOSsynchronous(clocked)FIFOmemorywhichsupportsclockfrequencies
up to 67 MHz and has read-access times as fast as 10 ns. The 64 x 36 dual-
port SRAM FIFO buffers data from port A to port B. The FIFO operates in IDT
Standard mode and has flags to indicate empty and full conditions, and two
programmableflags,Almost-Full(AF)andAlmost-Empty(AE),toindicatewhen
a selected number of words is stored in memory. FIFO data on port B can be
output in 36-bit, 18-bit, and 9-bit formats with a choice of Big- or Little-Endian
configurations.Threemodesofbyte-orderswappingarepossiblewithanybus-
sizeselection.CommunicationbetweeneachportcanbypasstheFIFOviatwo
FUNCTIONAL BLOCK DIAGRAM
Mail 2
Register
Mail 1
Register
Input
Register
Output
Register
64 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
Device
Control
RST
PEFA
MBF2
Port-B
Control
Logic
MBF1
EF
AE
36
B0 - B35
FF
AF
FS0
FS1
4661 drw 01
Programmable
Flag Offset
Registers
A0 - A35
Parity
Gen/Check
Parity
Generation
FIFO
ODD/
EVEN
PGA
Parity
Gen/Check
PGB
PEFB
36
RAM ARRAY
64 x 36
Bus-Matching
and
Byte
Swapping
Output
Register
CLKB
CSB
W/
RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
Port-B
Control
Logic
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IDT72V3614L12PF8 功能描述:IC FIFO 64X36X2 12NS 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
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