參數(shù)資料
型號: IDT72V3613L20PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 23/25頁
文件大?。?/td> 0K
描述: IC FIFO CLOCK 64X36 20NS 120TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 同步
存儲容量: 2.3K(64 x 36)
數(shù)據(jù)速率: 50MHz
訪問時間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V3613L20PF8
7
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3613L15
Symbol
Parameter
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
66.7
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
15
ns
tCLKH
Pulse Duration, CLKA and CLKB HIGH
6
ns
tCLKL
Pulse Duration, CLKA and CLKB LOW
6
ns
tDS
Setup Time, A0-A35 before CLKA
↑ and B0-B35 before CLKB↑
4–
ns
tENS
Setup Time, CSA, W/RA, ENA, and MBA before CLKA
↑; CSB, W/RB, and ENB before CLKB↑
5–
ns
tSZS
Setup Time, SIZ0, SIZ1, and BE before CLKB
4–
ns
tSWS
Setup Time, SW0 and SW1 before CLKB
6–
ns
tPGS
Setup Time, ODD/EVEN and PGB before CLKB
(1)
4–
ns
tRSTS
Setup Time, RST LOW before CLKA
↑ or CLKB↑(2)
5–
ns
tFSS
Setup Time, FS0 and FS1 before RST HIGH
5
ns
tDH
Hold Time, A0-A35 after CLKA
↑ and B0-B35 after CLKB↑
1–
ns
tENH
Hold Time, CSA W/RA, ENA and MBA after CLKA
↑; CSB, W/RB, and ENB after CLKB↑
1–
ns
tSZH
Hold Time, SIZ0, SIZ1, and BE after CLKB
2–
ns
tSWH
Hold Time, SW0 and SW1 after CLKB
2–
ns
tPGH
Hold Time, ODD/EVEN and PGB after CLKB
(1)
0–
ns
tRSTH
Hold Time, RST LOW after CLKA
↑ or CLKB↑(2)
5–
ns
tFSH
Hold Time, FS0 and FS1 after RST HIGH
4
ns
tSKEW1(3) Skew Time, between CLKA
↑ and CLKB↑ for EF and FF
8–
ns
tSKEW2(3,4) Skew Time, between CLKA
↑ and CLKB↑ for AE and AF
14
ns
NOTES:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
Commercial: Vcc=3.3V± 0.30V; TA = 0
°C to +70°C; JEDEC JESD8-A compliant
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