IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS" />
參數(shù)資料
型號(hào): IDT72V3644L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 33/34頁(yè)
文件大小: 0K
描述: IC FIFO 2048X36 15NS 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 72K(2K x 36)
數(shù)據(jù)速率: 67MHz
訪問(wèn)時(shí)間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱(chēng): 72V3644L15PF8
8
COMMERCIALTEMPERATURERANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3624L10(1)
IDT72V3624L15
IDT72V3634L10(1)
IDT72V3634L15
IDT72V3644L10(1)
IDT72V3644L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
100
66.7
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
10
15
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
4.5
6
ns
tCLKL
Pulse Duration, CLKA and CLKB LOW
4.5
6
ns
tDS
Setup Time, A0-A35 before CLKA
↑ and B0-B35 before CLKB↑
3—
4
ns
tENS1
Setup Time
CSA before CLKA
↑; CSB beforeCLKB↑4
4.5
ns
tENS2
Setup Time ENA, W/
RA and MBA before CLKA
↑; ENB, W/RB and MBB
3
4.5
ns
before CLKB
tRSTS
Setup Time,
MRS1, MRS2, PRS1, or PRS2 LOW before CLKA
↑ or CLKB↑(2)
5—
5
ns
tFSS
Setup Time, FS0 and FS1 before
MRS1 and MRS2 HIGH
7.5
7.5
ns
tBES
Setup Time, BE/
FWFT before MRS1 and MRS2 HIGH
7.5
7.5
ns
tSPMS
Setup Time,
SPM before MRS1 and MRS2 HIGH
7.5
7.5
ns
tSDS
Setup Time, FS0/SD before CLKA
3—
4
ns
tSENS
Setup Time, FS1/
SEN before CLKA
3—
4
ns
tFWS
Setup Time, BE/
FWFT before CLKA
0—
0
ns
tDH
Hold Time, A0-A35 after CLKA
↑and B0-B35 after CLKB↑
0.5
1
ns
tENH
Hold Time,
CSA, W/RA, ENA, and MBA after CLKA
↑; CSB, W/RB, ENB, and
0.5
1
ns
MBB after CLKB
tRSTH
Hold Time,
MRS1, MRS2, PRS1 or PRS2 LOW after CLKA
↑ or CLKB↑(2)
4—
4
ns
tFSH
Hold Time, FS0 and FS1 after
MRS1 and MRS2 HIGH
2
2
ns
tBEH
Hold Time, BE/
FWFT after MRS1 and MRS2 HIGH
2
2
ns
tSPMH
Hold Time,
SPM after MRS1 and MRS2 HIGH
2
2
ns
tSDH
Hold Time, FS0/SD after CLKA
0.5
1
ns
tSENH
Hold Time, FS1/
SEN HIGH after CLKA
0.5
1
ns
tSPH
Hold Time, FS1/
SEN HIGH after MRS1 and MRS2 HIGH
2
2
ns
tSKEW1(3)
Skew Time between CLKA
↑ and CLKB↑ for EFA/ORA, EFB/ORB, FFA/IRA,
5
7.5
ns
and
FFB/IRB
tSKEW2(3,4)
Skew Time between CLKA
↑ and CLKB↑ for AEA, AEB, AFA, and AFB
12
12
ns
NOTES:
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0
° to +70°C; JEDEC JESD8-A compliant.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
5. Industrial temperature range is available by special order.
Commercial: VCC = 3.3V +/- 0.30V; for 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V ; TA = 0
°Cto +70°C; JEDEC JESD8-A compliant
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