Figure 1. Typical Char" />
參數(shù)資料
型號: IDT72V3651L20PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 18/21頁
文件大?。?/td> 0K
描述: IC SYNCFIFO 2048X36 20NS 120TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 異步,同步
存儲容量: 72K(2K x 36)
數(shù)據(jù)速率: 520Mbs
訪問時間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V3651L20PF8
6
COMMERCIALTEMPERATURERANGE
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO 512 x 36, 1,024 x 36 and 2,048 x 36
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3641 with CLKA and CLKB set
to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize
the graph to a zero-capacitance load. Once the capacitance load per data-output channel and the number of IDT72V3631/72V3641/72V3651 inputs driven
by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) +
Σ(CL x VCC2 x fO)
N
where:
N = number of outputs = 36
CL = outputcapacitanceload
fO = switching frequency of an output
When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by:
PT = VCC x fS x 0.025 mA/MHz
0
10
20
3040
5060
70
0
25
50
75
100
125
150
VCC = 3.3V
fS
Clock Frequency
MHz
ICC(f)
Supply
Current
mA
fdata = 1/2 fS
TA = 25
°C
CL = 0 pF
VCC = 3.0V
VCC = 3.6V
4658 drw 04
175
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