IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
參數(shù)資料
型號(hào)： IDT72V3653L15PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 5/30頁(yè)
文件大?。?/td> 0K
描述： IC SYNCFIFO 2048X36 15NS 128TQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 72K（2K x 36）
數(shù)據(jù)速率： 67MHz
訪問時(shí)間： 15ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
其它名稱： 72V3653L15PF8
13
COMMERCIALTEMPERATURERANGE
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
synchronized to CLKB. Table 4 shows the relationship of each port flag to the
number of words stored in memory.
EMPTY/OUTPUT READY FLAGS (
EF/OR)
These are dual purpose flags. In the FWFT mode, the Output Ready
(OR) function is selected. When the Output-Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
IntheIDTStandardmode,theEmptyFlag(
EF)functionisselected. When
the Empty Flag is HIGH, data is available in the FIFO’s memory for reading to
the output register. When the Empty Flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
that reads data from its array (CLKB). For both the FWFT and IDT Standard
modes, the FIFO read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls an Output Ready flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReadyflag
synchronizingclock.Therefore,anOutputReadyflagisLOWifawordinmemory
is the next data to be sent to the FlFO output register and three cycles of the port
Clock that reads data from the FIFO have not elapsed since the time the word
waswritten. TheOutputReadyflagoftheFIFOremainsLOWuntilthethirdLOW-
to-HIGHtransitionofthesynchronizingclockoccurs,simultaneouslyforcingthe
Output Ready flag HIGH and shifting the word to the FIFO output register.
In IDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flag will indicate the presence of data available for reading in a minimum of two
cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW
if a word in memory is the next data to be sent to the FlFO output register and
twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince
the time the word was written. The Empty Flag of the FIFO remains LOW until
the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing
the Empty Flag HIGH; only then can data be read.
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 11 and 12).
FULL/INPUT READY FLAGS (
FF/IR)
This is a dual purpose flag. In FWFT mode, the Input Ready (IR) function
is selected. In IDT Standard mode, the Full Flag (
FF) functionisselected. For
both timing modes, when the Full/Input Ready flag is HIGH, a memory location
is free in the FIFO to receive new data. No memory locations are free when
the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array (CLKA). For both FWFT and IDT Standard modes, each
timeawordiswrittentoaFIFO,itswritepointerisincremented. Thestatemachine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock. Therefore,anFull/InputReadyflagisLOWiflessthantwo
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
nextmemorywritelocationhasbeenread. ThesecondLOW-to-HIGHtransition
ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input
Ready flag HIGH.
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock
begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 13 and 14).
ALMOST-EMPTY FLAG (
AE)
The Almost-Empty flag of a FIFO is synchronized to the port clock that
reads data from its array (CLKB). The state machine that controls an Almost-
Empty flag monitors a write pointer and read pointer comparator that indicates
when the FIFO memory status is almost-empty, almost-empty+1, or almost-
empty+2. TheAlmost-EmptystateisdefinedbythecontentsofregisterX. These
registersareloadedwithpresetvaluesduringaFIFOreset,programmedfrom
Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag
offset programming section). An Almost-Empty flag is LOW when its FIFO
contains X or less words and is HIGH when its FIFO contains (X+1) or more
words. NotethatadatawordpresentintheFIFOoutputregisterhasbeenread
frommemory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing
clockarerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenew
leveloffill. Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormore
words remains LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An Almost-Empty flag
is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock
after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transitionofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchro-
nizationcycleifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFO
to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle. (See Figure 15).
ALMOST-FULL FLAG (
AF)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
data to its array. The state machine that controls an Almost-Full flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2. TheAlmost-Fullstate
is defined by the contents of register Y. These registers are loaded with preset
values during a FlFO reset or, programmed from Port A, or programmed
serially (see Almost-Empty flag and Almost-Full flag offset programming
section). An Almost-Full flag is LOW when the number of words in its FIFO is
greaterthanorequalto(2,048-Y),(4,096-Y),or(8,192-Y)fortheIDT72V3653,
IDT72V3663, or IDT72V3673 respectively. An Almost-Full flag is HIGH when
the number of words in its FIFO is less than or equal to [2,048-(Y+1)],
[4,096-(Y+1)], or [8,192-(Y+1)] for the IDT72V3653, IDT72V3663, or
IDT72V3673 respectively. Note that a data word present in the FIFO output
register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
are required after a FIFO read for its Almost-Full flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing [2,048/4,096/8,192-
(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
not elapsed since the read that reduced the number of words in memory to
[2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the FIFO read that
reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)]. A
LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the
firstsynchronizationcycleifitoccursattimetSKEW2orgreaterafterthereadthat
reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)].
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle (see Figure 16).
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