IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
參數(shù)資料
型號(hào)： IDT72V3653L15PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 6/30頁(yè)
文件大?。?/td> 0K
描述： IC SYNCFIFO 2048X36 15NS 128TQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 72K（2K x 36）
數(shù)據(jù)速率： 67MHz
訪問時(shí)間： 15ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
其它名稱： 72V3653L15PF8
14
COMMERCIALTEMPERATURERANGE
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT72V3653/72V3663/72V3673
to pass command and control information between Port A and Port B without
putting it in queue. The Mailbox select (MBA, MBB) inputs choose between a
mail register and a FIFO for a port data transfer operation. The usable width
ofboththeMail1andMail2RegistersmatchestheselectedbussizeforPortB.
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen
a Port A write is selected by
CSA, W/RA, and ENA with MBA HIGH. If the
selectedPortBbussizeis36bits,theusablewidthoftheMail1Registeremploys
datalinesA0-A35.IftheselectedPortBbussizeis18bits,thentheusablewidth
of the Mail1 Register employs data lines A0-A17. (In this case, A18-A35 are
don’t care inputs.) If the selected Port B bus size is 9 bits, then the usable width
oftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,A9-A35aredon’t
care inputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
Register when a Port B write is selected by
CSB, W/RB, and ENB with MBB
HIGH. If the selected Port B bus size is 36 bits, the usable width of the Mail2
employs data lines B0-B35. If the selected Port B bus size is 18 bits, then the
usablewidthoftheMail2RegisteremploysdatalinesB0-B17.(Inthiscase,B18-
B35aredon’tcareinputs.)IftheselectedPortBbussizeis9bits,thentheusable
widthoftheMail2RegisteremploysdatalinesB0-B8.(Inthiscase,B9-B35are
don’t care inputs.)
Writing data to a mail register sets its corresponding flag (
MBF1 or
MBF2)LOW.Attemptedwritestoamailregisterareignoredwhilethemailflag
isLOW.
When data outputs of a port are active, the data on the bus comes from
the FIFO output register when the port Mailbox select input is LOW and from
the mail register when the port Mailbox select input is HIGH.
The Mail1 Register Flag (
MBF1) is set HIGH by a LOW-to-HIGH
transition on CLKB when a Port B read is selected by
CSB, W/RB, and ENB
with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on
B0-B35. For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17.
(Inthiscase,B18-B35areindeterminate.)Fora9-bitbussize,9bitsofmailbox
data are placed on B0-B8. (In this case, B9-B35 are indeterminate.)
The Mail2 Register Flag (
MBF2) is set HIGH by a LOW-to-HIGH
transition on CLKA when a Port A read is selected by
CSA, W/RA, and ENA
with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
The data in a mail register remains intact after it is read and changes only
whennewdataiswrittentotheregister.TheEndianselectfeaturehasnoeffect
on mailbox data. For mail register and mail register flag timing diagrams, see
Figure 17 and 18.
BUS SIZING
The Port B bus can be configured in a 36-bit long word, 18-bit word, or
9-bit byte format for data read from the FIFO. The levels applied to the Port B
BusSizeselect(SIZE)andtheBus-Matchselect(BM)determinethePortBbus
size. These levels should be static throughout FIFO operation. Both bus size
selectionsareimplementedatthecompletionofReset,bythetimetheFull/Input
Ready flag is set HIGH, as shown in Figure 2.
TwodifferentmethodsforsequencingdatatransferareavailableforPort
B when the bus size selection is either byte-or word-size. They are referred
to as Big-Endian (most significant byte first) and Little-Endian (least significant
bytefirst). ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW-
to-HIGH transition of
RS1selectstheendianmethodthatwillbeactiveduring
FIFO operation. BE is a don’t care input when the bus size selected for Port
B is long word. The endian method is implemented at the completion of Reset,
by the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
Only 36-bit long word data is written to or read from the FIFO memory on
the IDT72V3653/72V3663/72V3673. Bus-matching operations are done after
data is read from the FIFO RAM. These bus-matching operations are not
available when transferring data via mailbox registers. Furthermore, both the
word- and byte-size bus selections limit the width of the data bus that can be used
for mail register operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The remaining data
outputs will be indeterminate. The remaining data inputs will be don’t care inputs.
For example, when a word-size bus is selected, then mailbox data can be
transmitted only between A0-A17 and B0-B17. When a byte-size bus is
selected, then mailbox data can be transmitted only between A0-A8 and B0-
B8. (See Figures 17 and 18).
BUS-MATCHING FIFO READS
Data is read from the FIFO RAM in 36-bit long word increments. If a long
word bus size is implemented, the entire long word immediately shifts to the FIFO
output register. If byte or word size is implemented on Port B, only the first one
or two bytes appear on the selected portion of the FIFO output register, with the
rest of the long word stored in auxiliary registers. In this case, subsequent FIFO
reads output the rest of the long word to the FIFO output register in the order
shown by Figure 2.
When reading data from FIFO in byte or word format, the unused B0-B35
outputsareindeterminate.
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