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參數(shù)資料
| 型號： | IDT72V51256L7-5BBI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 42/56頁 |
| 文件大小： | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 標準包裝： | 1 |
| 類型： | 多隊列流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應商設備封裝： | 256-BGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 72V51256L7-5BBI |
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47
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
RCLK
OE
tOLZ
REN
RADEN
ESTR
WRADD
tAH
000 001
tAS
RDADD
D0Q1
D0 Q1
111 xxx
Device 7
110 010
*A*
*B*
*C*
*D*
*E*
*F*
000 xxx
tQH
tQS
tQH
tQS
tAH
tAS
tSTH
tSTS
tSTH
tSTS
5937 drw30
*AA*
xx0x
Device 0
PAFn
Bus
PAFn
*BB*
*CC*
*DD*
*EE*
*FF*
tPAFLZ
xx1x
Device 0
tPAF
xx0x
Device 0
xx1x
Device 0
Device 0 xx0x
Previous Device
Prev.
PAFn
Previous Device
tPAFHZ
HIGH-Z
Device 0
PAF
HIGH - Z
tPAFLZ
tWAF
Qout
D6Q2
WX
Prev. Q
WD-M+1
tA
FSTR
tA
WCLK
tSKEW3
WX +1
Prev. Q
12
D0 Q1
WEN
tENS
WADEN
tQH
tQS
tAH
tAS
tAH
tAS
WD - M + 2
tA
*G*
tA
D0 Q1
W0
D6 Q2
tENH
Din
tDS
tDH
tDS
tDH
tDS
tDH
Word Wy
D0 Q1
Wy+1
D0 Q1
Wy+2
D0 Q1
Device 0
Figure 27.
PAFn - Direct Mode, Flag Operation – Devices in Expansion
Cycle:
*A*
Queue 1 of device 0 is selected for read operations.
The last word in the output register is available on Qout.
OE was previously taken LOW so the output bus is in Low-Impedance.
*AA* Device 0 is selected for the
PAFn bus. The bus is currently providing status of a previously selected device X.
*B*
Word, Wx+1 is read out from the previous queue due to the FWFT effect.
*BB* Queue 1 of device 0 is selected on the write port.
The
PAFn bus is updated with the device selected on the previous cycle, device 0 PAF[1] is LOW showing the status of queue 1.
The
PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
*C*
Device 7 is selected for the
PAFn bus.
Word, Wd-m+1 is read from Q1 D0 due to the FWFT operation. This read is at the
PAFn boundary of queue D0 Q1. This read will cause the PAF[1] output to go from
LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.
*CC*
PAFn continues to show status of D0.
*D*
No read operations occur,
REN is HIGH.
*DD*
PAF[1] goes HIGH to show that D0 Q1 is not almost empty due to the read on cycle *C*.
The active queue
PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q1.
*E*
Queue 2 of Device 6 is selected for write operations.
*EE* Word, Wy+1 is written into D0 Q1.
*F*
Word, Wd-m+2 is read out due to FWFT operation.
*FF*
PAF[1] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q1 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q1.
*G*
Word, W0 is read from Q0 of D6, selected on cycle *E*, due to FWFT.
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| IDT72V51333L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51333L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51333L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51333L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
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