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參數(shù)資料
| 型號(hào)： | IDT72V70840DA |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SW 4096X4096 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | 72V |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 32:32 |
| 獨(dú)立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 72V70840DA |
5
COMMERCIALTEMPERATURERANGE
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
LOOPBACK CONTROL
Theloopbackcontrol(LPBK)bitofeachconnectionmemorylocationallows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TXn channel m routes to
the RXn channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
DELAY THROUGH THE IDT72V70840
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
ties on a per-channel basis. For voice applications, variable throughput delay
isbestasitensureminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
information is maintained through the switch.
The delay through the device varies according to the type of throughput
delay selected in the
V/C bit of the connection memory.
VARIABLE DELAY MODE (
V/C BIT = 0)
In this mode, the delay is dependent only on the combination of source and
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V70840 is three time-slots. If the input
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
be output in the following frame (channel n, frame p+1). The same is true if the
input channel n is switched to output channel n+1 or n+2. If the input channel
n is switched to output channel n+3, n+4,..., the new output data will appear in
thesameframe.Table2showsthepossibledelaysfortheIDT72V70840inthe
variable delay mode.
CONSTANT DELAY MODE (
V/C BIT = 1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V70840, the minimum throughput delay achievable in the constant
delaymodewillbeoneframe.Forexample,wheninputtime-slot31isswitched
tooutputtime-slot0.Themaximumdelayof94time-slotsofdelayoccurswhen
time-slot 0 in a frame is switched to time-slot 31 in the frame.
MICROPROCESSOR INTER.ACE
The IDT72V70840’s microprocessor interface looks like a standard RAM
interface to improve integration into a system. With a 12-bit address bus and
a16-bitdatabus,readandwritesaremappeddirectlyintoDataandConnection
memories and require only one cycle to access. By allowing the internal
memoriestoberandomlyaccessedinonecycle,thecontrollingmicroprocessor
has more time to manage other peripheral devices and can more easily and
quickly gather information and setup the switch paths.
Table 4 shows the mapping of the addresses into internal memory blocks
and Table 5 shows the Control Register information.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal
registers and memories of the IDT72V70840.
Thetwomostsignificantbitsoftheaddressselectbetweentheregisters,Data
Memory,andConnectionMemory. IfA13andA12areHIGH,A11-A0areused
toaddresstheDataMemory. IfA13isHIGHandA12isLOW,A11-A0areused
to address Connection Memory. If A13 is LOW and A12 is HIGH A11-A0 are
usedtoselecttheControlRegister,FrameAlignmentRegister,andFrameOffset
Registers. See Table 4 for mappings.
As explained in the Serial Data Interface Timing and Switching Configura-
tions sections, after system power-up, the Control Register should be pro-
grammed immediately to establish the desired switching configuration.
ThedataintheControlRegisterconsistsoftheMemoryBlockProgramming
bit (MBP), the Block Programming Data (BPE) bits, the Begin Block Program-
mingEnable(BPE),theOutputStandBy,StartFrameEvaluation,andDataRate
Select bits. As explained in the Memory Block Programming section, the BPE
begins the programming if the MBP bit is enabled. This allows the entire
connectionmemoryblocktobeprogrammedwiththeBlockProgrammingData
bits. If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all
TX output drivers. If the ODE pin is high, the contents of the OSB bit is ignored
and all TX output drivers are enabled.
CONNECTION MEMORY CONTROL
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
location controls the output drivers-enables (if high) or disables (if low). See
Table 3 for detail.
TheProcessorChannel(PC)bitoftheConnectionMemoryselectsbetween
ProcessorModeandConnectionMode. Ifhigh,thecontentsoftheConnection
Memory are output on the TX streams. If low, the Stream Address Bit (SAB)
and the Channel Address Bit (CAB) of the Connection Memory defines the
sourceinformation(streamandchannel)ofthetime-slotthatwillbeswitchedto
the output from Data Memory.
Also in the Connection Memory is the
V/C (Variable/Constant Delay) bit.
Each Connection Memory location allows the per-channel selection between
variable and constant throughput delay modes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RXn channel m data comes from the
TXn channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION O. THE IDT72V70840
After power up, the state of the connection memory is unknown. As such,
theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.
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| IDT72V70840DAG | 功能描述:IC DGTL SW 4096X4096 144-TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 信號(hào)開關(guān)，多路復(fù)用器，解碼器 系列:72V 標(biāo)準(zhǔn)包裝:48 系列:74VHC 類型:多路復(fù)用器 電路:4 x 2:1 獨(dú)立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| IDT72V71623BC | 功能描述:IC DGTL SW 2048X2048 144-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號(hào)開關(guān)，多路復(fù)用器，解碼器 系列:72V 標(biāo)準(zhǔn)包裝:48 系列:74VHC 類型:多路復(fù)用器 電路:4 x 2:1 獨(dú)立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
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| IDT72V71623BCG | 功能描述:IC DGTL SW 2048X2048 144-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 信號(hào)開關(guān)，多路復(fù)用器，解碼器 系列:72V 標(biāo)準(zhǔn)包裝:48 系列:74VHC 類型:多路復(fù)用器 電路:4 x 2:1 獨(dú)立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
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