參數(shù)資料
型號(hào): IDT72V815L10PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 8/26頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 512X18 10NS 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 9.2K(512 x 18)
數(shù)據(jù)速率: 100MHz
訪問時(shí)間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 72V815L10PF8
16
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009
NOTES:
1. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset.
WCLK
tENS
tENH
WEN
HF
tENS
RCLK
REN
4295 drw 15
D/2 words in FIFO(2),
[
+ 1
] words in FIFO(3)
D-1
2
D/2 + 1 words in FIFO
(2),
[
+ 2
] words in FIFO(3)
D-1
2
D/2 words in FIFO(2),
[
+ 1
] words in FIFO(3)
D-1
2
tHF
tCLKL
tCLKH
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
3.
PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
WCLK
tCLKH
tCLKL
tENS
tENH
WEN
PAF
tENS
tPAFA
D - (m + 1) words
in FIFO
RCLK
tPAFA
REN
(1)
4295 drw 14
D - m words
in FIFO
D - (m + 1) words in FIFO
Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes)
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