參數(shù)資料
型號: IDT72V845L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/26頁
文件大小: 0K
描述: IC FIFO SYNC 4096X18 128QFP
標準包裝: 1,000
系列: 72V
功能: 異步,同步
存儲容量: 72K(4K x 18)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 72V845L15PF8
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
13
FEBRUARY 11, 2009
NO OPERATION
RCLK
REN
EF
t ENS
tENH
VALID DATA
t OLZ
Q0 - Q17
OE
WCLK
WEN
4295 drw 07
t CLK
t CLKH
t CLKL
tREF
tA
t OE
t OHZ
SKEW1
t
(1)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH during the current clock cycle. If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then
EF may not change state until the next RCLK edge.
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
WCLK
D0 - D17
WEN
RCLK
EF
Q0 - Q17
REN
t DS
t ENS
t REF
0
12
3
D
DDD
01
DD
(first valid write)
OE
D4
tENS
4295 drw 08
tSKEW1
tFRL(1)
t OLZ
t OE
tA
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (
EF = LOW).
2. The first word is available the cycle after
EF goes HIGH, always.
3. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 8. First Data Word Latency with Single Register-Buffered
EF
EF (IDT Standard Mode)
Figure 7. Read Cycle Timing with Single Register-Buffered
EF
EF (IDT Standard Mode)
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IDT72V845L15PFGI 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 4096X18 128QFP
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