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參數(shù)資料
| 型號： | IDT72V85L20PAGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO |
| 中文描述： | 3.3伏CMOS雙異步FIFO |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 151K |
| 代理商： | IDT72V85L20PAGI |
1
DSC-3966/2
JULY 2006
IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85
3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
DUAL 512 x 9, DUAL 1,024 x 9
DUAL 2,048 x 9, DUAL 4,096 X 9
DUAL 8,192 X 9
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The AsyncFIFO
is a trademark of Integrated Device Technology, Inc.
COMMERICAL TEMPERATURE RANGE
FEATURES:
The IDT72V81 is equivalent to two IDT72V01 - 512 x 9 FIFOs
The IDT72V82 is equivalent to two IDT72V02 - 1,024 x 9 FIFOs
The IDT72V83 is equivalent to two IDT72V03 - 2,048 x 9 FIFOs
The IDT72V84 is equivalent to two IDT72V04 - 4,096 x 9 FIFOs
The IDT72V85 is equivalent to two IDT72V05 - 8,192 x 9 FIFOs
Low power consumption
— Active: 330 mW (max.)
— Power-down: 18 mW (max.)
Ultra high speed—15 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
Ideal for bidirectional, width expansion, depth expansion, bus-
matching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS technology
Space-saving TSSOP package
Industrial temperature range (–40
°
C to +85
°
C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72V81/72V82/72V83/72V84/72V85 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional and
compatible to two IDT72V01/72V02/72V03/72V04/72V05 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflow and expansion logic to allow for unlimted expansion capability in both
word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (
W
) and Read
(
R
) pins.
The devices utilize a 9-bit wide data array to allow for control and parity
bits at the users option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmssion/reception
error checking. It also features a Retransmt (
RT
) capability that allows for reset
of the read pointer to its initial position when
RT
is pulsed low to allow for
retransmssion fromthe beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using IDT’s high-speed CMOS technology.
They are designed for those applications requiring asynchronous and simul-
taneous read/writes in multiprocessing and rate buffer applications.
FUNCTIONAL BLOCK DIAGRAM
WA
WRITE
CONTROL
READ
CONTROL
RA
FLAG
LOGIC
EXPANSION
LOGIC
XIA
WRITE
POINTER
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
READ
POINTER
DATA INPUTS
0
8
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
(QA
0
-QA
8
)
RSA
FLA
/
RTA
XOA
/
HFA
FFA
EFA
WB
WRITE
CONTROL
READ
CONTROL
RB
FLAG
LOGIC
EXPANSION
LOGIC
XIB
WRITE
POINTER
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
(QB
0
-QB
8
)
RSB
FLB
/
RTB
3966 drw 01
XOB
/
HFB
FFB
EFB
512 x 9
1,024 x 9
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