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參數(shù)資料
| 型號： | IDT72V85L20PAGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO |
| 中文描述： | 3.3伏CMOS雙異步FIFO |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 151K |
| 代理商： | IDT72V85L20PAGI |
8
COMMERCIAL TEMPERATURE RANGE
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
JULY 17, 2006
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the corresponding
input control signals of multiple FIFOs. Status flags (
EF
,
FF
and
HF
) can be
detected fromany one FIFO. Figure 13 demonstrates an 18-bit word width by
using the two FIFOs contained in the IDT72V81/72V82/72V83/72V84/72V85s.
Any word width can be attained by adding FIFOs (Figure 13).
Bidirectional Operation
Applications which require data buffering between two systems (each
systemcapable of Read and Write operations) can be achieved by pairing
IDT72V81/72V82/72V83/72V84/72V85s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permtted, a read flow-through
and write flow-through mode. For the read flow-through mode (Figure 17), the
FIFO permts a reading of a single word after writing one word of data into an
empty FIFO. The data is enabled on the bus in (t
WEF
+ t
A
) ns after the rising
edge of
W
, called the first write edge, and it remains on the bus until the
R
line
is raised fromlow-to-high, after which the bus would go into a three-state mode
after t
RHZ
ns. The
EF
line would have a pulse showing temporary deassertion
and then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permts the writing
of a single word of data immediately after reading one word of data froma
full FIFO. The
R
line causes the
FF
to be deasserted but the
W
line being low
causes it to be asserted again in anticipation of a new data word. On the rising
edge of
W
, the new word is loaded in the FIFO. The
W
line must be toggled when
FF
is not asserted to write new data in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be applied together
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
Figure 12. Block Diagram of One 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 FIFO Used in Single Device Mode
Figure 13. Block Diagram of One 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18 FIFO Memory Used in Width Expansion Mode
XIA
XIB
9
9
18
9
18
HFB
HFA
9
WRITE (
W
)
FULL FLAG (
FFA
)
RESET (
RS
)
READ (
R
)
EMPTY FLAG (
EFB
)
RETRANSMIT (
RT
)
DATA
OUT
(Q)
3966 drw 15
FIFO A
FIFO B
72V81/72V82/72V83
72V84/72V85
DATA
(D)
IN
WRITE (
W
)
DATA IN (D)
FULL FLAG (
FF
)
RESET (
RS
)
9
READ (
R
)
9
DATA OUT (Q)
EMPTY FLAG (
EF
)
RETRANSMIT (
RT
)
EXPANSION IN (
XI
)
(
HF
)
IDT
72V81
72V82
72V83
72V84
72V85
(HALF-FULL FLAG)
3966 drw 14
FIFO
A or B
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