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| 型號(hào)： | IDT73720PQF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | 16-BIT TRI-PORT BUS EXCHANGER |
| 中文描述： | 73 SERIES, 16-BIT EXCHANGER, TRUE OUTPUT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 74K |
| 代理商： | IDT73720PQF |
IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
11.5
3
PIN DESCRIPTION
Signal
X(0:15)
Y(0:15)
Z(0:15)
LEXY
I/O
I/O
I/O
I/O
I
Description
Bidirectional Data Port X. Usually connected to the CPU's A/D (Address/Data) bus.
Bidirectional Data port Y. Connected to the even path or even bank of memory.
Bidirectional Data port Z. Connected to the odd path or odd bank of memory.
Latch Enable input for Y-Write Latch. The Y-Write Latch is open when LEXY is HIGH. Data from the X-port
(CPU) is latched on the HIGH-to-LOW transition of LEXY
Latch Enable input for Z-Write Latch. The Z-Write Latch is open when LEXZ is HIGH. Data from the X-port
(CPU) is latched on the HIGH-to-LOW transition of LEXZ.
Latch Enable input for the Y-Read Latch. The Y-Read Latch is open when LEYX is HIGH. Data from the even
path Y is latched on the HIGH-to-LOW transition of LEYX.
Latch Enable input for the Z-Read Latch. The Z-Read Latch is open when LEZX is HIGH. Data from the odd
path Z is latched on the HIGH-to-LOW transition of LEZX
Even/Odd Path Selection. When high, PATH enables data transfer between the X-Port and the Y-port (even
path). When LOW, PATH enables data transfer between the X-Port and the Z-Port (odd path).
Transmit/Receive Data. When high, Port X is an input Port and either Port Y or Z is an output Port. When LOW,
Port X is an output Port while Ports Y & Z are input Ports
Output Enable for Upper byte. When LOW, the Upper byte of data is transfered to the port specified by PATH in
the direction specified by T/
R
.
LEXZ
I
LEYX
I
LEZX
I
PATH
I
T/
R
I
OEU
I
OEL
I
Output Enable for Lower byte. When LOW, the Lower byte of data is transfered to the port specified by PATH in
the direction specified by T/
R
.
2527 tbl 02
CAPACITANCE
(T
A
= +25
°
C, F = 1.0MH
Z
)
Parameter
(1)
C
IN
Input Capacitance
C
OUT
Output Capacitance
Symbol
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
12
Unit
pF
pF
NOTE:
1. This parameter is guaranteed by device characterization, but is not prod-
uction tested.
2527 tbl 04
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Com’l.
–0.5 to +7.0
Mil.
Unit
V
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power
Dissipation
DC Output
Current
–0.5 to +7.0
T
A
0 to +70
–55 to +125
°
C
T
BIAS
–55 to +125
–65 to +135
°
C
T
STG
–55 to +125
–65 to +125
°
C
P
T
1.0
1.0
W
I
OUT
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2527 tbl 03
TRUTH TABLE
Path
L
L
H
H
T/
R
L
H
L
H
OEU
L
L
L
L
OEL
L
L
L
L
Functionality
Z
→
X (16-bits)–Read Z
(1)
X
→
Z (16 bits)–Write Z
(1)
Y
→
X (16-bits)–Read Y
(2)
X
→
Y (16 bits)–Write Y
(2)
All output buffers are
disabled
Transfer of lower 8 bits
(0:7) as per PATH & T/
R
X
X
H
H
X
X
H
L
X
X
L
H
Transfer of upper 8 bits
(8:15) as per PATH & T/
R
NOTES:
1. For Z
→
X and X
→
Z transfers, Y-port output buffers are tristated.
2. For Y
→
X and X
→
Y transfers, Z-port output buffers are tristated.
2527 tbl 01
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