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參數(shù)資料
| 型號： | IDT74ALVCH16903PAG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 12-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | GREEN, TSSOP-56 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 133K |
| 代理商： | IDT74ALVCH16903PAG |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
1
JUNE 2006
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-4911/4
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in TSSOP package
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL
BUS DRIVER WITH PARITY
CHECKER, DUAL 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This 12-bit universal bus driver is built using advanced dual metal CMOS
technology. This device has dual outputs and can operate as a buffer or an
edge-triggered register. In both modes, parity is checked on APAR, which
arrives one cycle after the data to which it applies. The
YERRoutput,whichis
produced one cycle after APAR, is open drain.
MODE selects one of the two data paths. When MODE is low, the device
operates as an edge-triggered register. On the positive transition of the clock
(CLK) input and when the clock-enable (
CLKEN)inputislow,datasetupatthe
A inputs is stored in the internal registers. On the positive transition of CLK and
when
CLKEN is high, only data setup at the 9A-12A inputs is stored in their
internalregisters.WhenMODEishigh,thedeviceoperatesasabufferanddata
at the A inputs passes directly to the outputs. The 11A/
YERREN servesadual
purpose; it acts as a normal data bit and also enables
YERRdatatobeclocked
into the
YERR outputregister.
When used as a single device, parity output enable (
PAROE) must be tied
high;whenparityinput/output(PARI/O)islow,evenparityisselectedandwhen
PARI/O is high, odd parity is selected. When used in pairs and
PAROEislow,
the parity sum is output on PARI/O for cascading to the second ALVCH16903.
When used in pairs and
PAROE is high, PARI/O accepts a partial parity sum
from the first ALVCH16903.
Abufferedoutput-enable(
OE)inputcanbeusedtoplacethe24outputsand
YERRineitheranormallogicstate(highorlowlogiclevels)orahigh-impedance
state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebuslines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup components.
The ALVCH16903 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16903 has “bus-hold” which retains the inputs’ last state
whenevertheinputbusgoestoahigh-impedance.Thispreventsfloatinginputs
and eliminates the need for pull-up/down resistors.
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to +4.6
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
(Outputs Only)
TSTG
Storage Temperature
–65 to +150
° C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
±50
mA
VI < 0 or VI > VCC
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. This value is limited to 4.6V maximum.
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance
VOUT = 0V
7
9
pF
COUT
I/O Port Capacitance
VIN = 0V
7
9
pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
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