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參數(shù)資料
| 型號： | IDT74FCT388915T100PY |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 145K |
| 代理商： | IDT74FCT388915T100PY |
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.8
2
PIN CONFIGURATIONS
PLCC/LCC
TOP VIEW
PIN DESCRIPTION
Pin Name
SYNC(0)
SYNC(1)
SSOP
TOP VIEW
3052 drw 03
5
6
7
8
9
10
11
V
CC
OE/RST
FEEDBACK
REF_SEL
SYNC(0)
V
CC
(AN)
1
2
3
4
20
19
18
17
16
15
14
13
Q4
V
CC
2Q
12
GND
Q5
Q/2
GND
Q3
V
CC
LF
Q2
GND
LOCK
GND(AN)
SO28-7
21
22
23
24
SYNC(1)
FREQ_SEL
GND
Q0
V
CC
Q1
GND
PLL_EN
25
26
27
28
O
V
C
Q
G
Q
V
C
2
Q/2
GND
Q3
V
CC
Q2
GND
LOCK
P
G
Q
V
C
Q
G
F
FEEDBK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
SYNC(1)
28
4
3
2
1
27
26
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12
13
14
15
16
17
18
J28-1,
L28-1
3052 drw 02
I/O
I
I
Description
Reference clock input.
Reference clock input.
REF_SEL
FREQ_SEL
FEEDBACK
I
I
I
Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).
Selects between
÷
1 and
÷
2 frequency options. (Refer to functional block diagram).
Feedback input to phase detector.
LF
Q0-Q4
Q5
I
Input for external loop filter connection.
Clock output.
Inverted clock output.
O
O
2Q
Q/2
LOCK
O
O
O
Clock output (2 x Q frequency).
Clock output (Q frequency
÷
2).
Indicates phase lock has been achieved (HIGH when locked).
OE/
RST
I
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are
enabled. When LOW, outputs are in HIGH impedance.
Disables phase-lock for low frequency testing. (Refer to functional block diagram).
PLL_EN
I
3052 tbl 01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT388915T100PYB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T133 | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T133J | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T133JB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T133L | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FCT388915T150PY | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT388915T70J | 制造商:Integrated Device Technology Inc 功能描述:EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER, 28 Pin, Plastic, PLCC |
| IDT74FCT388915T70PY | 制造商:Integrated Device Technology 功能描述:74FCT 70MHz 10 to 70MHz Tray |
| IDT74FCT388915TBJG | 功能描述:IC PLL CLK GENERATOR 3ST 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:74FCT 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT74FCT388915TBJG8 | 功能描述:IC PLL CLK GENERATOR 3ST 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:74FCT 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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