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參數(shù)資料
| 型號(hào)： | IDT74FCT88915TT133PY8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | IDT74FCT88915TT133PY8 |
5
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIALTEMPERATURERANGE
Symbol
Parameter
Condition(1)
Min.
Max.
Unit
tRISE/FALL
Rise/Fall Time
CL = 50pF
1(2)
2.5
ns
All Outputs
(between 0.2 VCC and 0.8 VCC )RL = 500
Ω
tRISE/FALL
Rise/Fall Time
CL = 20pF &
0.5(2)
1.6
ns
2QOutput(3)
(between 0.8V and 2.0V)
termination(7)
tPULSEWIDTH
Output Pulse Width
CL = 50pF
0.5tCYCLE–0.5(5)
0.5tCYCLE + 0.5(5)
ns
Q,
Q, Q/2 Outputs(3)
Q0-Q4,
Q5, Q/2 @ VCC/2
tPULSEWIDTH
Output Pulse Width
CL = 50pF
0.5tCYCLE – 1(5)
0.5tCYCLE + 1(5)
ns
2QOutput(3)
2Q Output @ VCC/2
tPULSEWIDTH
Output Pulse Width
Terminationasin
0.5tCYCLE – 0.5(5)
0.5tCYCLE + 0.5(5)
ns
2QOutput(3)
2Q @ 1.5V
note7
tPD
SYNC input to FEEDBACK delay
Load = 50
Ω to VCC/2,
–0.5
+0.5
ns
SYNC-FEEDBACK(3)
(measured at SYNC0 or 1 and FEEDBACK
CL = 20pF
inputpins)
0.1MF from LF to Analog GND(9)
tSKEWr
Output to Output Skew between outputs 2Q,
CL = 50pF
—
500
ps
(rising)(3,4)
Q0-Q4,Q/2 (rising edges only)
tSKEWf
Output to Output Skew between outputs 2Q,
—
500
ps
(falling)(3,4)
Q0-Q4 (falling edges only)
tSKEWALL(3,4)
Output to Output Skew
—
500
ps
2Q, Q/2, Q0-Q4 rising,
Q5 falling
tLOCK(6)
Time required to acquire Phase-Lock from time
1(2)
10
ms
SYNC input signal is received
tRST
Propagation Delay,
RST (HIGH-to-LOW) to any
1.5(2)
8ns
Reset – Q
Output (HIGH-to-LOW)
tREC(10)
Reset Recovery Time
9
—
ns
Rising
RST edge to falling SYNC edge
tW(10)
Minimum Pulse Width
RST input LOW
5
—
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, CL = 50pF (±2pF), and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q,
Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1F, tLOCK Min. is with C1 = 0.01F (where C1 is loop filter
capacitor shown in Figure 2).
7. These two specs ( tRISE/FALL and tPULSE WIDTH 2Q output) guarantee that the FCT88915TT meets 68040 P-Clock input specification. For these two specs to be guaranteed
by IDT, the termination scheme shown in Figure 1 must be used:
Rp
Zo (clock trace)
Rp = 1.5 Zo
Rs = Zo - 7
Ω
68040
P-Clock
Input
88915TT
2Q
Output
Rs
Figure 1. MC68040 P-Clock Input Termination Scheme
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| IDT74FCT88915TT70PY | 功能描述:IC PLL CLK GENERATOR 28-SSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:74FCT 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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