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參數(shù)資料
| 型號： | IDT74FCT88915TT70PY8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | IDT74FCT88915TT70PY8 |
1
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIALTEMPERATURERANGE
MARCH 2001
IDT74FCT88915TT
55/70/100/133
COMMERCIAL TEMPERATURE RANGE
LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
DESCRIPTION:
The FCT88915TT uses phase-lock loop technology to lock the frequency
and phase of outputs to the input reference clock. It provides low skew clock
distribution for high performance PCs and workstations. One of the outputs is
fed back to the PLL at the FEEDBACK input resulting in essentially zero delay
across the device. The PLL consists of the phase/frequency detector, charge
pump, loop filter and VCO. The VCO is designed to run optimally between
20MHz and f2Q Max.
TheFCT88915TTprovideseightoutputswith500psskew. The
Q5outputis
invertedfromtheQoutputs. The2QrunsattwicetheQfrequencyandQ/2 runs
at half the Q frequency.
The FREQ_SEL control provides an additional ÷ 2 option in the output path.
PLL_ENallowsbypassingofthePLL,whichisusefulinstatictestmodes. When
PLL_EN is low, SYNC input may be used as a test clock. In this test mode, the
input frequency is not limited to the specified range and the polarity of outputs
is complementary to that in normal operation (PLL_EN = 1). The LOCK output
attains logic high when the PLL is in steady-state phase and frequency lock.
The FCT88915TT requires external loop filter components as recom-
mended in Figure 2.
Phase/Freq.
Detector
M
u
x
0
1
SYNC (0)
FEEDBAC K
SYNC (1)
REF_SEL
PLL_EN
Mux
01
Divide
-By-2
(
÷ 1)
(
÷ 2)
1
0
M
u
x
Charge Pum p
Voltage
Controlled
Oscilator
RST
FREQ _SEL
2Q
Q0
Q1
Q2
Q3
Q4
Q5
Q/2
D
Q
CP
Q
R
D
Q
CP
Q
R
D
Q
CP
R
D
Q
CP
R
D
Q
CP
R
D
Q
CP
R
D
Q
CP
R
D
Q
CP
LF
LO CK
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2001 Integrated Device Technology, Inc.
DSC-4245/4
FEATURES:
0.5 MICRON CMOS Technology
Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
Max. output frequency: 133MHz
Pin and function compatible with MC88915
Five non-inverting outputs, one inverting output, one 2x
output, one ÷2 output; all outputs are TTL-compatible
Output Skew < 500ps (max.)
Duty cycle distortion < 500ps (max.)
Part-to-part skew: 0.55ns (from tPD max. spec)
64/–15mA drive at TTL output voltage levels
Available in PLCC and SSOP packages
FUNCTIONAL BLOCK DIAGRAM
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