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參數(shù)資料
| 型號： | IDT74FCT88915TT70PY8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | IDT74FCT88915TT70PY8 |
8
COMMERCIALTEMPERATURERANGE
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Inthisapplication,theQ/2outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q/2 and SYNC. Thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4,
Q5) will
always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2
frequency.
ThefrequencyrelationshipshownhereisapplicabletoallQoutputs(Q0,Q1,
Q2, Q3 and Q4).
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
In this application, the 2Q output is connected to the FEEDBACK input. The
internal PLL will line up the positive edges of 2Q and SYNC. Thus the 2Q
frequency will equal the SYNC frequency. The Q/2 output will always run at
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
Figure 4c. Wiring Diagram and Frequency Relationships
with 2Q Output Feedback
Allowable Input Frequency Range:
10MHz to (f2Q FMAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q FMAX Spec)/8 (for FREQ_SEL LOW)
Figure 4a. Wiring Diagram and Frequency Relationships
with Q/2 Output Feedback
Allowable Input Frequency Range:
20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q FMAX Spec)/4 (for FREQ_SEL LOW)
Figure 4b. Wiring Diagram and Frequency Relationships
with Q4 Output Feedback
Allowable Input Frequency Range:
40MHz to (f2Q FMAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL LOW)
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
In this application, the Q4 output is connected to the FEEDBACK input. The
internal PLL will line up the positive edges of Q4 and SYNC. Thus the Q4
frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The
Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run
at 2X the Q frequency.
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEED BACK
REF_SEL
SYNC(0)
VCC(AN)
LF
GND(AN)
Q4
Q5
2Q
LO W
50 MHz signal
12.5 M Hz feedback signal
HIG H
HIGH
25 MHz
"Q"
Clock
Outputs
12.5 M Hz
input
RST
FCT88915TT
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEEDBACK
REF_SEL
SYNC(0)
VCC(AN)
LF
GND(AN
)
Q4
Q5
2Q
FCT88915T
T
LOW
50 MHz signal
25 MHz feedback signal
HIGH
25 MHz
"Q"
Clock
Outputs
25 MHz
input
12.5 MHz
signal
RST
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ _SEL
FEED BAC K
REF_SEL
SYN C(0)
VCC(AN)
LF
GN D(AN)
Q4
Q5
2Q
FCT88915TT
LO W
50 MH z feedback signal
HIG H
HIGH
25 MH z
"Q"
Clock
O utputs
50 M Hz
input
12.5 M Hz
input
RST
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