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參數(shù)資料
| 型號： | IDT74GTLP16612PA8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | GTLP SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 72K |
| 代理商： | IDT74GTLP16612PA8 |
3
IDT74GTLP16612
CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIALTEMPERATURERANGE
FUNCTIONAL DESCRIPTION:
The GTLP16612 combines a universal transceiver function with a TTL
to GTLP translation. The A-Port and control pins operate at LVTTL or 5V
TTL levels while the B-Port operates at GTLP levels. The transceiver logic
includes D-type latches and D-type flip-flops to allow data flow in transparent,
latched, and clock mode.
RECOMMENDEDOPERATING
CONDITIONS(1)
Symbol
Rating
Recommended
Unit
VCC
Supply Voltage
3.15 to 3.45
V
VCCQ
4.75 to 5.25
VTT
BusTerminationVoltage
1.35 to 1.65
V
VI
Input Voltage on A-Port and Control Pins
0 to 5.5
V
IOH
HIGH Level Output Current (A-Port)
-32
mA
IOL
LOW Level Output Current (A-Port)
+32
mA
IOL
LOW Level Output Current (B-Port)
+34
mA
TA
OperatingTemperature
–40 to +85
° C
NOTE:
1.
Unused inputs without Bus-Hold must be held HIGH or LOW.
FUNCTION TABLE(1,2)
Inputs
Outputs
Mode
CEAB
OEAB
LEAB
CLKAB
Ax
Bx
X
H
X
Z
Latched
LL
L
H
X
B
0
(3)
storage
LL
L
X
B
0
(4)
of A data
X
L
H
X
L
Transparent
XL
H
X
H
LL
L
↑
L
Clocked storage
LL
L
↑
H
of A data
HL
L
X
B
0
(4)
Clock Inhibit
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGH Transition
2. A-to-B data flow is shown. B-to-A data flow is similar, but uses
OEBA, LEBA, CLKBA, and CEBA.
3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
4. Output level before the indicated steady-state input conditions were established.
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