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參數(shù)資料
| 型號： | IDT77301L12PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| 中文描述： | 128 X 9 OTHER FIFO, 10 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 4/29頁 |
| 文件大?。?/td> | 342K |
| 代理商： | IDT77301L12PF |
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IDT77301
UtopiaFIFO 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO Commercial and Industrial Temperature Ranges
4
)*&+
Symbol
Name
I/O
Description
54, 56
Data 9-10 /
P_ID 0-1
I
18-Bit bus: Data bus input
9-bit bus: Parallel programmable register load (ID0, ID1)
57-64, 66
Data 0-8
I
Data bus input
68
I
Reset. Clears all FIFO memory locations, cell size read/write pointers.
69-73
ADR0-4
I
Address Location(s). Provide cell destination and multicast addresses. Singlecast Operation: for out-
band routing, address location is loaded fromincomng Utopia Level 2 compliant address lines; for
in-band routing, address location is derived fromdata lines D0-D17 (see Table 1a). Multicast
Operation for out-band routing, the ADR0-3 signals (ADR4 is not used) act as enables which select
the desired output FIFO combination (see Table 1b); for in-band routing, the output FIFO
combindation is derived fromthe data lines D0-D17.
74
BSS
I
Bus Size Select. BSS HIGH, the input bus is set to 9-bits (D0-D8) and D9-D17 determne cell size
and chip ID. BSS LOW the input bus is 18-bits.
67
WCLK
I
Input port Data write clock.
76
BNE
I
Byte Nibble Enable. BNE HIGH, output ports are byte wide data buses. BNE LOW output data is in
4-bit "nibble" increments using Q0-Q3. This mode supports wde input data bus applications of 32 to
72-bit wdths.
77
MAS
I
Multicast/Address Select. Determnes single or multicast input mode. Selecting MAS HIGH sets the
device to multicast mode with ADR0-3 as enables. MAS LOW the device is set to single destination
mode wth ADR0-4 lines as address lines.
78
RMS
I
Routing Method Select. With RMS HIGH, In-band Routing is selected. With RMS LOW Out-band
Routing is selected.
79
MSE
I
Master Slave Enable. With MSE set HIGH, device is set as a master; with MSE LOW device is set
as a slave.
80
I
Serial Load Enable.
81
SCLK
I
Serial Load Clock.
82
SDI/P_ID0
I
BSS low Serial data load. BSS high Serial input port for loading programmable registers.
83
I
Output Enable. Tri-States all data output buses.
84
RCLK
I
Data read clock.
86-90,
92-95
DATA-a
O
Data bus output for FIFO-a. Master Mode wth BNE HIGH: output is a 9-bit word. Master Mode wth
BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the lowand
high nibble transfer Slave Mode wth BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the lowand high nibble transfer
96
SOCS-1
O
Start Of Cell (FIFO-a) output fromUtopiaFIFO. Active on first byte of data transfer SOCS deasserts for
all remaining byte transfers.
98
CLAVS-a
I
Cell Available (FIFO-a). CLAVS notifies the UtopiaFIFO port. A cell transfer can be initiated by
the port.
99
-s
I/O
Enable (FIFO-a). Master Mode:
place on the current clock cycle. Slave Mode:
data nibble (Q0-3) on the output bus on the next read clock edge.
is an active lowoutput. When asserted, a data transfer wll take
is an input which causes the fifo port to update a
GND
____
Logic and supply ground pins 9, 21, 33, 45, 55, 75, 85 and 97.
V
CC
____
Logic and supply V
CC
pins 3, 15, 27, 39, 65, and 91.
3240 tbl 02
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