參數(shù)資料
型號(hào)： IDT79RC32T351-133DHG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 3/42頁(yè)
文件大小： 0K
描述： IC MPU 32BIT CORE 133MHZ 208-QFP
產(chǎn)品變化通告： Product Discontinuation 07/Dec/2009
標(biāo)準(zhǔn)包裝： 24
系列： Interprise™
處理器類(lèi)型： RISC 32-位
速度： 133MHz
電壓： 2.5V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
包裝： 托盤(pán)
其它名稱(chēng)： 79RC32T351-133DHG
11 of 42
May 25, 2004
IDT 79RC32351
Boot Configuration Vector
The boot configuration vector is read into the RC32351 during cold reset. The vector defines parameters in the RC32351 that are essential to oper-
ation when cold reset is complete.
The encoding of boot configuration vector is described in Table 2, and the vector input is illustrated in Figure 6.
U0DTRN
O
Low Drive UART channel 0 data terminal ready.
Primary function: General Purpose I/O, GPIOP[4]. At reset, this pin defaults to primary function GPIOP[4] if CPU/DMA Sta-
tus Mode enable is not selected during reset using the boot configuration.
2nd Alternate function: CPU or DMA transaction indicator, CPUP.
U0DSRN
I
STI
UART channel 0 data set ready.
Primary function: General Purpose I/O, GPIOP[5]. At reset, this pin defaults to primary function GPIOP[5].
U0RTSN
O
Low Drive UART channel 0 request to send.
Primary function: General Purpose I/O, GPIOP[6]. At reset, this pin defaults to primary function GPIOP[6].
U0CTSN
I
STI
UART channel 0 clear to send.
Primary function: General Purpose I/O, GPIOP[7]. At reset, this pin defaults to primary function GPIOP[7].
U0SOUTP
O
Low Drive UART channel 1 serial transmit.
Primary function: General Purpose I/O, GPIOP[8]. At reset, this pin defaults to primary function GPIOP[8] if DMA Debug
enable is not selected during reset using the boot configuration.
2nd Alternate function: DMA channel, DMAP[3].
U1SINP
I
STI
UART channel 1 serial receive.
Primary function: General Purpose I/O, GPIOP[9]. At reset, this pin defaults to primary function GPIOP[9] if DMA Debug
enable is not selected during reset using the boot configuration.
2nd Alternate function: DMA channel, DMAP[2].
U1DTRN
O
Low Drive UART channel 1 data terminal ready.
Primary function: General Purpose I/O, GPIOP[10]. At reset, this pin defaults to primary function GPIOP[10] if ICE Interface
enable is not selected during reset using the boot configuration.
Alternate function: PC trace status bit 0, EJTAG_PCST[0].
U1DSRN
I
STI
UART channel 1 data set ready.
Primary function: General Purpose I/O, GPIOP[11]. At reset, this pin defaults to primary function GPIOP[11] if ICE Interface
enable is not selected during reset using the boot configuration.
2nd Alternate function: PC trace status bit 1, EJTAG_PCST[1].
U1RTSN
O
Low Drive UART channel 1 request to send.
Primary function: General Purpose I/O, GPIOP[12]. At reset, this pin defaults to primary function GPIOP[12] if ICE Interface
enable is not selected during reset using the boot configuration.
2nd Alternate function: PC trace status bit 2, EJTAG_PCST[2].
U1CTSN
I
STI
UART channel 1 clear to send.
Primary function: General Purpose I/O, GPIOP[13]. At reset, this pin defaults to primary function GPIOP[13] if ICE Interface
enable is not selected during reset using the boot configuration.
2nd Alternate function: PC trace clock, EJTAG_DCLK.
1. Schmitt Trigger Input.
Name
Type I/O Type
Description
Table 1 Pin Descriptions (Part 7 of 7)
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