參數(shù)資料
型號(hào): IDT79RC32T351-133DHG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 9/42頁
文件大小: 0K
描述: IC MPU 32BIT CORE 133MHZ 208-QFP
產(chǎn)品變化通告: Product Discontinuation 07/Dec/2009
標(biāo)準(zhǔn)包裝: 24
系列: Interprise™
處理器類型: RISC 32-位
速度: 133MHz
電壓: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
其它名稱: 79RC32T351-133DHG
17 of 42
May 25, 2004
IDT 79RC32351
Figure 6 Cold Reset AC Timing Waveform
BOOT VECT
SYSCLKP
COLDRSTN
RSTN
MDATA[31:0]
BDIRN
BOEN[0]
>= 100 ms
>=10ms
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
*
>= 4096 CLKP clock cycles
OR
>= 64 CLKP clock cycles
*
* Selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset).
Tpw1
Tdo2
CLKP
1
FFFF_FFFF
Thld3
1. COLDRSTN asserted by external logic.
2. The RC32351 asserts RSTN, asserts BOEN[0] low, drives BDIRN low, and tri-states the data bus in response.
3. External logic begins driving valid boot configuration vector on the data bus, and the RC32351 starts sampling it.
4. External logic negates COLDRSTN and tri-states the boot configuration vector on MDATA[15:0]. The boot configuration vector must not be
tri-stated before COLDRSTN is deasserted. The RC32351 stops sampling the boot configuration vector.
5. The RC32351 starts driving the data bus, MDATA[31:0], deasserts BOEN[0] high, and drives BDIRN high.
6. SYSCLKP may be held constant after this point if Hold SYSCLKP Constant is selected in the boot configuration vector.
7. RSTN negated by RC32351.
8. CPU begins executing by taking MIPS reset exception, and the RC32351 starts sampling RSTN as a warm reset input.
2
34
5
6
7
8
Trise1
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