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參數(shù)資料
| 型號： | IDT82P2282PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 312/381頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX T1/J1/E1 2CHAN 100-TQFP |
| 標準包裝： | 15 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2282PF |
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
38
August 20, 2009
3.8.1.2
Error Event And Out Of Synchronization Detection
After the frame is in synchronization, the Frame Processor contin-
ues to monitor the received data stream to detect errors and judge if it is
out of synchronization.
3.8.1.2.1
Super Frame (SF) Format
In SF format, two kinds of errors are detected:
1. Severely Ft Bit Error: Each received Ft bit is compared with the
expected one (refer to Table 12). Each unmatched Ft bit leads to an Ft
bit error event. When 2 or more Ft bit errors are detected in a 6-basic-
frame fixed window, the severely Ft bit error occurs. This error event is
captured by the SFEI bit.
2. F Bit Error: Each received F bit is compared with the expected
one (refer to Table 12). Each unmatched F bit leads to an F bit error
event. This error event is captured by the FERI bit and is forwarded to
the Performance Monitor.
When the F Bit Error number exceeds the ratio set in the M2O[1:0]
bits, it is out of synchronization. Then if the REFEN bit is ‘1’, the Frame
Processor will start to search for synchronization again. If the REFEN bit
is ‘0’, no error can lead to reframe except for manually setting. The man-
ual reframe is executed by a transition from ‘0’ to ‘1’ on the REFR bit.
During out of synchronization state, the error event detection is sus-
pended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.2.2
Extended Super Frame (ESF) Format
In ESF format, four kinds of errors are detected:
1. Frame Alignment Bit Error: Each received Frame Alignment bit is
compared with the expected one (refer to Table 13). Each unmatched bit
leads to a frame alignment bit error event. This error event is captured
by the FERI bit and is forwarded to the Performance Monitor.
2. CRC-6 Error: When the local calculated CRC-6 of the current
received ESF frame does not match the received CRC-6 of the next
received ESF frame, a single CRC-6 error event is generated. This error
event is captured by the BEEI bit and is forwarded to the Performance
Monitor.
3. Excessive CRC-6 Error: Once the accumulated CRC-6 errors
exceed 319 occasions (> 319) in a 1 second fixed window, an excessive
CRC-6 error event is generated. This error event is captured by the
EXCRCERI bit and is forwarded to the Performance Monitor.
4. Severely Frame Alignment Bit Error: When 2 or more frame
alignment bit errors are detected in a 1-ESF-frame fixed window, the
severely frame alignment bit error occurs. This error event is captured
by the SFEI bit.
When the Frame Alignment Bit Error number exceeds the ratio set
in the M2O[1:0] bits, it is out of synchronization. Then if the REFEN bit is
‘1’, the Frame Processor will start to search for synchronization again.
Additionally, the Excessive CRC-6 Error also leads to out of ESF syn-
chronization. In this condition, both the REFEN bit being ‘1’ and the
REFCRCE bit being ‘1’ will allow the Frame Processor to search for syn-
chronization again. If the REFEN bit is ‘0’, no error can lead to reframe
except for manually setting. The manual reframe is executed by a transi-
tion from ‘0’ to ‘1’ on the REFR bit. During out of synchronization state,
the error event detection is suspended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.2.3
T1 Digital Multiplexer (DM) Format (T1 only)
In T1 DM format, three kinds of errors are detected:
1. Severely Ft Bit Error: Each received Ft bit is compared with the
expected one (refer to Table 14). Each unmatched Ft bit leads to an Ft
bit error event. When 2 or more Ft bit errors are detected in a 6-basic-
frame fixed window, the severely Ft bit error occurs. This error event is
captured by the SFEI bit.
2. F Bit Error: Each received F bit is compared with the expected
one (refer to Table 14). Each unmatched F bit leads to an F bit error
event. This error event is captured by the FERI bit and is forwarded to
the Performance Monitor.
3. DDS Pattern Error: The received 6-bit DDS in each CH24 is
compared with the DDS pattern - ‘0XX11101’ (MSB left and ‘X’ is not
cared). When one or more bits do not match the DDS pattern, a single
DDS pattern error event is generated. This error event is forwarded to
the Performance Monitor.
The 6-bit DDS pattern and its following F-bit make up a 7-bit pat-
tern. When one or more bits do not match its pattern (refer to Table 14),
a single error is generated. When this error number exceeds the ratio
set in the M2O[1:0] bits, it is out of synchronization. Then if the REFEN
bit is ‘1’, the Frame Processor will start to search for synchronization
again. If the REFEN bit is ‘0’, no error can lead to reframe except for
manually setting. The manual reframe is executed by a transition from
‘0’ to ‘1’ on the REFR bit. During out of synchronization state, the error
event detection is suspended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.2.4
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
In SLC-96 format, only one kind of error is detected:
1. F Bit Error: The Ft bit in each odd frame and the Fs bit in Frame
(2n) (0<n<12 and n=36) is compared with the expected one (refer to
Table 15). Each unmatched bit leads to a F-bit error event. This error
event is captured by the FERI bit and is forwarded to the Performance
Monitor.
Each unmatched Ft bit in the odd frame and each unmatched Fs bit
in Frame (2n) (0<n<12 and n=36) are also counted separately. When the
number of either of them exceeds the ratio set in the M2O[1:0] bits, it is
out of synchronization. Then if the REFEN bit is ‘1’, the Frame Proces-
sor will start to search for synchronization again. If the REFEN bit is ‘0’,
no error can lead to reframe except for manually setting. The manual
reframe is executed by a transition from ‘0’ to ‘1’ on the REFR bit. During
out of synchronization state, the error event detection is suspended.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2282PF8 | 功能描述:TXRX T1/J1/E1 2CHAN 100-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2282PFBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Dual T1/E1/J1 Long Haul / Short Haul Transceiver |
| IDT82P2282PFG | 功能描述:IC TXRX T1/J1/E1 2CH 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:2,500 系列:- 類型:驅動器 驅動器/接收器數(shù):4/0 規(guī)程:RS422 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC N 包裝:帶卷 (TR) |
| IDT82P2282PFG8 | 功能描述:TXRX T1/J1/E1 2CHAN 100-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2282PFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Dual T1/E1/J1 Long Haul / Short Haul Transceiver |
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