參數(shù)資料
型號(hào)： IDT82P2282PFG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 350/381頁(yè)
文件大?。?/td> 0K
描述： IC TXRX T1/J1/E1 2CH 100TQFP
標(biāo)準(zhǔn)包裝： 15
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： T1/E1/J1
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x20）
包裝： 托盤(pán)
其它名稱： 82P2282PFG
IDT82P2282PFG-ND
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
70
August 20, 2009
In Non-multiplexed mode, the channel offset can be configured
from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the
channel offset can be configured from 0 to 127 channels (0 & 127 are
included).
3.17.1.5
Output On RSDn/MRSD & RSIGn/MRSIG
The output on the RSDn/MRSD and the RSIGn/MRSIG pins can be
configured by the TRI bit of the corresponding link to be in high imped-
ance state or to output the processed data stream.
3.17.2
E1 MODE
In E1 mode, the Receive System Interface can be set in Non-multi-
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
RSDn pin is used to output the received data from each link at the bit
rate of 2.048 Mb/s. While in the Multiplexed Mode, the received data
from the two links is byte interleaved to form one high speed data stream
and output on the MRSD pin at the bit rate of 8.192 Mb/s.
In the Non-multiplexed mode, if the RSCK is from outside, the
receive system interface is in Receive Clcok Slave mode, otherwise if
the device outputs clock to RSCK from itself, the receive system inter-
face is in Receive Clcok Master mode.
In the Receive Clock Master mode, if RSCKn outputs pulses during
the entire E1 frame, the Receive System Interface is in Receive Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on RSCKn, the Receive System Interface is in Receive Clock
Master Fractional E1 mode.
Table 40 summarizes how to set the receive system interface of
each link into various operating modes and the pins’ direction of the
receive system interface in different operating modes.
3.17.2.1
Receive Clock Master Mode
In the Receive Clock Master mode, each link uses its own timing
signal on the RSCKn pin and framing pulse on the RSFSn pin to output
the data on each RSDn pin. The signaling bits on the RSIGn pin are per-
timeslot aligned with the data on the RSDn pin.
In the Receive Clock Master mode, the data on the system inter-
face is clocked by the RSCKn. The active edge of the RSCKn used to
update the pulse on the RSFSn is determined by the FE bit. The active
edge of the RSCKn used to update the data on the RSDn and RSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFSn is ahead.
In the Receive Clock Master mode, the RSFSn can indicate the
Basic frame, CRC Multi-frame, Signaling Multi-frame, or both the CRC
Multi-frame and Signaling Multi-frame, or the TS1 and TS 16 overhead.
All the indications are selected by the OHD bit, the SMFS bit and the
CMFS bit. The active polarity of the RSFSn is selected by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full E1 mode and Receive Clock Master Fractional E1
mode.
3.17.2.1.1
Receive Clock Master Full E1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame is clocked out by the RSCKn.
3.17.2.1.2
Receive Clock Master Fractional E1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
The RSCKn is gapped during the timeslots or the Bit 8 duration by
selecting the G56K & GAP bits in the Receive Payload Control. The data
in the corresponding gapped duration is a don't care condition.
3.17.2.2
Receive Clock Slave Mode
In the Receive Clock Slave mode, the timing signal on the RSCKn
pin and framing pulse on the RSFSn pin to output the data on the RSDn
pin are provided by the system side. When the RSLVCK bit is set to ‘0’,
each link uses its own RSCKn and RSFSn; when the RSLVCK bit is set
to ‘1’ and both two links are in the Receive Clock Slave mode, the two
links use the RSCK[1] and RSFS[1] to output the data. The signaling bits
Table 40: Operating Modes Selection In E1 Receive Path
RMUX RMODE G56K, GAP
Operating Mode
Receive System Interface Pin
Input
Output
0
00
Receive Clock Master Full E1
X
RSCKn, RSFSn, RSDn, RSIGn
not both 0s 1 Receive Clock Master Fractional E1
1
X
Receive Clock Slave
RSCKn, RSFSn
RSDn, RSIGn
1
X
Receive Multiplexed
MRSCK, MRSFS
MRSD, MRSIG
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
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IDT82P2282PFG8 功能描述:TXRX T1/J1/E1 2CHAN 100-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82P2282PFGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Dual T1/E1/J1 Long Haul / Short Haul Transceiver
IDT82P2282PK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Dual T1/E1/J1 Long Haul / Short Haul Transceiver
IDT82P2284 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Quad T1/E1/J1 Long Haul / Short Haul Transceiver
IDT82P2284BB 功能描述:TXRX T1/J1/E1 4CHAN 208-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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