參數(shù)資料
型號(hào)： IDT82P2288BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 數(shù)字傳輸電路
英文描述： Octal T1/E1/J1 Long Haul Short Haul Transceiver
中文描述： DATACOM, PCM TRANSCEIVER, PBGA256
封裝： PLASTIC, BGA-256
文件頁(yè)數(shù)： 66/375頁(yè)
文件大小： 2430K
代理商： IDT82P2288BB
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
55
October 7, 2003
Figure 19. T1/J1 To E1 Format Mapping - Continuous Channels Mode
In the Receive Clock Slave mode, the timing signal on the RSCK
pin and the framing pulse on the RSFS pin to output the data on the
RSD pin are provided by the system side. The signaling bits on the
RSIG pin are per-channel aligned with the data on the RSD pin.
In the Receive Clock Slave mode, the data on the system interface
is clocked by the RSCK. The active edge of the RSCK used to sample
the pulse on the RSFS is determined by the FE bit. The active edge of
the RSCK used to update the data on the RSD and RSIG is determined
by the DE bit. If the FE bit and the DE bit are not equal, the pulse on the
RSFS is ahead. The data rate of the system side is 1.544 Mb/s or 2.048
Mb/s. When it is 2.048 Mb/s, the RSCK can be selected by the CMS bit
to be the same rate as the data rate on the system side (2.048 MHz) or
double the data rate (4.096 MHz). If the speed of the RSCK is double
the data rate, there will be two active edges in one bit duration. In this
case, the EDGE bit determines the active edge to update the data on the
RSD and RSIG pins. The pulse on the RSFS pin is always sampled on
its first active edge.
In the Receive Clock Slave mode, the RSFS asserts at a rate of
integer multiple of 125
μ
s to indicate the start of a frame. The active
polarity of the RSFS is selected by the FSINV bit. If the pulse on the
RSFS pin is not an integer multiple of 125
μ
s, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the
INT
pin when the RCOFAI bit is ‘1’.
3.17.1.3
Receive Multiplexed Mode
In the Receive Multiplexed mode, since the received data should
be mapped to 2.048 Mb/s format first, the 3 kinds of schemes should be
selected by the MAP[1:0] bits. The mapping per G.802, per One Filler
Every Four CHs and per Continuous CHs are the same as the descrip-
tion in Chapter 3.17.1.2 Receive Clock Slave Mode.
In the Receive Multiplexed mode, a multiplexed bus is used to out-
put the data from the link. The data of the link is byte-interleaved output
on the multiplexed bus. When the data from the link is output on one
multiplexed bus, the position of the data is arranged by setting the chan-
nel offset.
In the Receive Multiplexed mode, the timing signal on the MRSCK
pin and the framing pulse on the MRSFS pin are provided by the system
side . The signaling bits on the MRSIG pin are per-channel aligned with
the corresponding data on the MRSD pin.
In the Receive Multiplexed mode, the data on the system interface
is clocked by the MRSCK. The active edge of the MRSCK used to sam-
ple the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSD and MRSIG
is determined by the DE bit. If the FE bit and the DE bit are not equal,
the pulse on the MRSFS is ahead. The MRSCK can be selected by the
CMS bit to be the same rate as the data rate on the system side (8.192
MHz) or double the data rate (16.384 MHz). If the speed of the MRSCK
is double the data rate, there will be two active edges in one bit duration.
In this case, the EDGE bit determines the active edge to update the data
on the MRSD and MRSIG pins. The pulse on the MRSFS pin is always
sampled on its first active edge.
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
integer multiple of 125
μ
s to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. If the pulse on the
MRSFS pin is not an integer multiple of 125
μ
s, this detection will be
indicated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt
will be reported by the
INT
pin when the RCOFAI bit is ‘1’.
3.17.1.4
Offset
Bit offset and channel offset are both supported in all the operating
modes. The offset is between the framing pulse on RSFS/MRSFS pin
and the start of the corresponding frame output on the RSD/MRSD pin.
The signaling bits on the RSIG/MRSIG pin are always per-channel
aligned with the data on the RSD/MRSD pin.
Figure 20 to Figure 23 show the base line without offset.
1.544
Mb/s
2.048
Mb/s
CH1
CH2
CH3
F
CH23
CH1
CH2
CH24
TS0
TS2
TS1
TS23
TS24
TS0
TS1
TS2
TS24
the 8th bit
CH24
TS3
TS25~TS31
the 8th bit
F
F
CH1
filler
filler
filler
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