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參數(shù)資料
| 型號(hào)： | IDT82P2288BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | Octal T1/E1/J1 Long Haul Short Haul Transceiver |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 69/375頁(yè) |
| 文件大?。?/td> | 2430K |
| 代理商： | IDT82P2288BB |
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
58
October 7, 2003
3.17.2
E1 MODE
In E1 mode, the Receive System Interface can be set in Non-multi-
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
RSD pin is used to output the received data at the bit rate of 2.048 Mb/s.
While in the Multiplexed Mode, the received data from the link is byte
interleaved to form one high speed data stream and output on the
MRSD pin at the bit rate of 8.192 Mb/s.
In the Non-multiplexed Mode, if the receive system interface and
the receive line side are timed to a same clock source, the Receive Sys-
tem Interface is in Receive Clock Master mode. If the receive system
interface and the receive line side are timed to different clock sources,
the Receive System Interface is in Receive Clock Slave mode.
In the Receive Clock Master mode, if RSCK outputs pulses during
the entire E1 frame, the Receive System Interface is in Receive Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on RSCK, the Receive System Interface is in Receive Clock
Master Fractional E1 mode.
Table 40 summarizes how to set the receive system interface into
various operating modes and the pins’ direction of the receive system
interface in different operating modes.
3.17.2.1
Receive Clock Master Mode
In the Receive Clock Master mode, the timing signal on the RSCK
pin and framing pulse on the RSFS pin are used to output the data on
the RSD pin. The signaling bits on the RSIG pin are per-timeslot aligned
with the data on the RSD pin.
In the Receive Clock Master mode, the data on the system inter-
face is clocked by the RSCK. The active edge of the RSCK used to
update the pulse on the RSFS is determined by the FE bit. The active
edge of the RSCK used to update the data on the RSD and RSIG is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFS is ahead.
In the Receive Clock Master mode, the RSFS can indicate the
Basic frame, CRC Multi-frame, Signaling Multi-frame, or both the CRC
Multi-frame and Signaling Multi-frame, or the TS1 and TS 16 overhead.
All the indications are selected by the OHD bit, the SMFS bit and the
CMFS bit. The active polarity of the RSFS is selected by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full E1 mode and Receive Clock Master Fractional E1
mode.
3.17.2.1.1
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCK is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame is clocked out by the RSCK.
Receive Clock Master Full E1 Mode
3.17.2.1.2
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCK is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
Receive Clock Master Fractional E1 Mode
The RSCK is gapped during the timeslots or the Bit 8 duration by
selecting the G56K & GAP bits in the Receive Payload Control. The data
in the corresponding gapped duration is a don't care condition.
3.17.2.2
Receive Clock Slave Mode
In the Receive Clock Slave mode, the timing signal on the RSCK
pin and framing pulse on the RSFS pin to output the data on the RSD
pin are provided by the system side. The signaling bits on the RSIG pin
are per-timeslot aligned with the data on the RSD pin.
In the Receive Clock Slave mode, the data on the system interface
is clocked by the RSCK. The active edge of the RSCK used to sample
the pulse on the RSFS is determined by the FE bit. The active edge of
the RSCK used to update the data on the RSD and RSIG is determined
by the DE bit. If the FE bit and the DE bit are not equal, the pulse on the
RSFS is ahead. The speed of the RSCK can be selected by the CMS bit
to be the same rate as the data rate on the system side (2.048 MHz) or
double the data rate (4.096 MHz). If the speed of the RSCK is double
the data rate, there will be two active edges in one bit duration. In this
case, the EDGE bit determines the active edge to update the data on the
RSD and RSIG pins. The pulse on the RSFS pin is always sampled on
its first active edge.
In the Receive Clock Slave mode, the RSFS asserts at a rate of
integer multiple of 125
μ
s to indicate the start of a frame. The active
polarity of the RSFS is selected by the FSINV bit. If the pulse on the
RSFS pin is not an integer multiple of 125
μ
s, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the
INT
pin when the RCOFAI bit is ‘1’.
Table 40: Operating Modes Selection In E1 Receive Path
RMUX
RMODE
G56K, GAP
Operating Mode
Receive System Interface Pin
Input
Output
0
0
00
Receive Clock Master Full E1
not both 0s
1
Receive Clock Master Fractional E1
X
Receive Clock Slave
X
Receive Multiplexed
X
RSCK, RSFS, RSD, RSIG
1
X
RSCK, RSFS
MRSCK, MRSFS
RSD, RSIG
1
MRSD, MRSIG
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
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