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參數資料
| 型號： | IDT82P2288BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 15/362頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX T1/J1/E1 8CHAN 256-PBGA |
| 標準包裝： | 10 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | IEEE 1149.1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應商設備封裝： | 256-PBGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2346 82P2288BB IDT82P2288BB-ND |
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IDT82P2288
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
111
March 04, 2009
3.27.2 LOOPBACK
System Loopback, Payload Loopback, Local Digital Loopback 1 & 2,
Remote Loopback and Analog Loopback are all supported in the
IDT82P2288. Their routes are shown in the Functional Block Diagram.
3.27.2.1 System Loopback
The System Loopback can only be implemented when the Receive
System Interface and the Transmit System Interface are in different
Non-multiplexed operating modes (one in Clock Master mode and the
other in Clock Slave mode). However, in T1/J1 mode, when either the
receive path or the transmit path is in T1/J1 mode E1 rate, the System
Loopback is not supported.
Distinguished by the loopback direction, the System Loopback can
be divided into System Remote Loopback and System Local Loopback.
When the data and signaling bits from the transmit path are looped to
the receive path, it is System Remote Loopback. When the data and
signaling bits from the receive path are looped to the transmit path, it is
System Local Loopback.
System Remote Loopback
Enabled by the SRLP bit, the System Remote Loopback is imple-
mented. The data and signaling bits to be transmitted on the TSDn and
TSIGn pins are internally looped to the RSDn and RSIGn pins. When
the receive path is in Receive Clock Master mode and the transmit path
is in Transmit Clock Slave mode, the clock signal and the framing pulse
from the system side on the TSCKn and TSFSn pins are looped to the
RSCKn and RSFSn pins respectively. When the transmit path is in
Transmit Clock Master mode and the receive path is in Receive Clock
Slave mode, the clock signal and the framing pulse from the system side
on the RSCKn and RSFSn pins are looped to the TSCKn and TSFSn
pins respectively.
In System Remote Loopback mode, the data stream to be trans-
mitted is still output to the line side, while the data stream received from
the line side is replaced by the System Remote Loopback data.
System Local Loopback
Enabled by the SLLP bit, the System Local Loopback is imple-
mented. The received data and signaling bits to be output on the RSDn
and RSIGn pins are internally looped to the TSDn and TSIGn pins.
When the receive path is in Receive Clock Master mode and the
transmit path is in Transmit Clock Slave mode, the recovered clock
signal and framing pulse on the RSCKn and RSFSn pins are looped to
the TSCKn and TSFSn pins respectively. When the transmit path is in
Transmit Clock Master mode and the receive path is in Receive Clock
Slave mode, the TSCKn and TSFSn pins are looped to the RSCKn and
RSFSn pins respectively.
In System Local Loopback mode, the data stream received from the
line side is still output to the system through the RSDn and RSIGn pins,
while the data stream to be transmitted through the TSDn and TSIGn
pins are replaced by the System Local Loopback data.
3.27.2.2 Payload Loopback
By programming the GSUBST[2:0] bits or the SUBST[2:0] bits, the
Payload Loopback can be implemented. The received data output from
the Elastic Store Buffer is internally looped to the Transmit Payload
Control.
In Payload Loopback mode, the received data is still output to the
system side, while the data to be transmitted from the system side is
replaced by the Payload Loopback data.
3.27.2.3 Local Digital Loopback 1
Enabled by the DLLP bit, the Local Digital Loopback 1 is imple-
mented. The data stream output from the Transmit Buffer is internally
looped to the Frame Processor.
In Local Digital Loopback 1 mode, the data stream to be transmitted
is still output to the line side, while the data stream received from the line
side is replaced by the Local Digital Loopback 1 data.
3.27.2.4 Remote Loopback
Enabled by the RLP bit, the Remote Loopback is implemented. The
data stream output from the optional Receive Jitter Attenuator is inter-
nally looped to the optional Transmit Jitter Attenuator.
In Remote Loopback mode, the data stream received from the line
side is still output to the system, while the data stream to be transmitted
is replaced by the Remote Loopback data.
3.27.2.5 Local Digital Loopback 2
Enabled by the DLP bit, the Local Digital Loopback 2 is implemented.
The data stream output from the optional Transmit Jitter Attenuator is
internally looped to the Optional Receive Jitter Attenuator.
In Local Digital Loopback 2 mode, the data stream to be transmitted
is still output to the line side, while the data stream received from the line
side is replaced by the Local Digital Loopback 2 data.
3.27.2.6 Analog Loopback
Enabled by the ALP bit, the Analog Loopback is implemented. The
data stream to be transmitted on the TTIPn/TRINGn pins is internally
looped to the RTIPn/RRINGn pins.
In Analog Loopback mode, the data stream to be transmitted is still
output to the line side, while the data stream received from the line side
is replaced by the Analog Loopback data.
If analog loopback is enabled, line driver should be set to normal
(T_HZ=0 & THZ pin is tied to ground).
3.27.3 G.772 NON-INTRUSIVE MONITORING
When the G.772 Non-Intrusive Monitoring is implemented, only
seven links are in normal operation and the Link 1 is configured to
monitor the receive path or transmit path of any of the remaining links.
Whether the G.772 Non-Intrusive Monitoring is implemented and
which direction (receive/transmit) and link is monitored are both deter-
mined by the MON[3:0] bits.
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相關代理商/技術參數 |
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| IDT82P2288BB8 | 功能描述:TXRX T1/J1/E1 8CHAN 256-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數:2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2288BBBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Octal T1/E1/J1 Long Haul / Short Haul Transceiver |
| IDT82P2288BBG | 功能描述:TXRX OCTAL T1/E1/J1 256-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數:2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2288BBG8 | 功能描述:TXRX T1/J1/E1 8CHAN 256-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數:2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2521 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(1) Channel High-Density E1 Line Interface Unit |
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